SLVSH18B December   2024  – July 2025 TPS4HC120-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics, SNS
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Current and Voltage Conventions
      2. 7.3.2 Low Power Mode
        1. 7.3.2.1 Entry into LPM
        2. 7.3.2.2 During LPM
        3. 7.3.2.3 Exiting LPM
      3. 7.3.3 Accurate Current Sense
      4. 7.3.4 Adjustable Current Limit
      5. 7.3.5 Inductive-Load Switching-Off Clamp
      6. 7.3.6 Fault Detection and Reporting
        1. 7.3.6.1 Diagnostic Enable Function
        2. 7.3.6.2 Multiplexing of Current Sense
        3. 7.3.6.3 FAULT Reporting
        4. 7.3.6.4 Fault Table
      7. 7.3.7 Full Diagnostics
        1. 7.3.7.1 Short-to-GND and Overload Detection
        2. 7.3.7.2 Open-Load Detection
          1. 7.3.7.2.1 Channel On
          2. 7.3.7.2.2 Channel Off
        3. 7.3.7.3 Short-to-Battery Detection
        4. 7.3.7.4 Reverse-Polarity and Battery Protection
        5. 7.3.7.5 Thermal Fault Detection
          1. 7.3.7.5.1 Thermal Protection Behavior
      8. 7.3.8 Full Protections
        1. 7.3.8.1 UVLO Protection
        2. 7.3.8.2 Loss of GND Protection
        3. 7.3.8.3 Loss of Power Supply Protection
        4. 7.3.8.4 Reverse Polarity Protection
        5. 7.3.8.5 Protection for MCU I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Modes
        1. 7.4.1.1 SLEEP
        2. 7.4.1.2 DIAGNOSTIC
        3. 7.4.1.3 ACTIVE
        4. 7.4.1.4 STANDBY DELAY
        5. 7.4.1.5 LOW POWER MODE
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 EMC Transient Disturbances Test
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
        1. 8.4.2.1 Without a GND Network
        2. 8.4.2.2 With a GND Network
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGQ|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.1 EMC Transient Disturbances Test

As a result of the severe electrical conditions in the automotive environment, immunity capacity against electrical transient disturbances is required, especially for a high-side power switch, which is connected directly to the battery. Detailed test requirements are in accordance with the ISO 7637-2:2011 and ISO 16750-2:2010 standards.

Table 8-1 ISO 7637-2:2011(E) in 12V System
TEST ITEM
(1)(2)		TEST PULSE SEVERITY LEVEL AND VS ACCORDINGLYPULSE DURATION (td)MINIMUM NUMBER OF PULSES OR TEST TIMEBURST-CYCLE PULSE-REPETITION TIMEINPUT RESISTANCE (Ω)FUNCTION PERFORMANCE STATUS CLASSIFICATION(3)

LEVEL

VS/VMINMAX
1III–1122ms500 pulses0.5s—10Status II
2aIII5550µs500 pulses0.2s5s2Status II
2bIV100.2s to 2s10 pulses0.5s5s0 to 0.05Status II
3aIV–2200.1µs1h90ms100ms50Status II
3bIV1500.1µs1h90ms100ms50Status II
(1) Tested both under input low condition and high condition.
(2) GND pin network is a 1kΩ resistor in parallel with a diode BAS21-7-F.
(3) Status II: The function does not perform as designed during the test, but returns automatically to normal operation after the test.
Table 8-2 ISO 16750-2:2010(E) Load Dump Test B in 12V System
TEST ITEM
(1)(2)(3)		TEST PULSE SEVERITY LEVEL AND VS ACCORDINGLYPULSE DURATION (td)MINIMUM NUMBER OF PULSES OR TEST TIMEBURST-CYCLE PULSE-REPETITION TIMEINPUT RESISTANCE (Ω)FUNCTION PERFORMANCE STATUS CLASSIFICATION(4)
LEVELVS/V
Test B

N/A

3540ms to 400ms5 pulses60s0.5 to 4Status II
(1) Tested both under input low condition and high condition (DIAG_EN, ENx, and VBB are all classified as inputs).
(2) Considering the worst test condition, the device is tested without any filter capacitors on VBB and VOUTx.
(3) The GND pin network is a 1kΩ resistor in parallel with a diode BAS21-7-F.
(4) Status II: The function does not perform as designed during the test, but returns automatically to normal operation after the test.