SLVSD45 December   2015 TPS50601-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  PVIN vs Frequency
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Adjusting the Output Voltage
      5. 8.3.5  Maximum Duty Cycle Limit
      6. 8.3.6  PVIN vs Frequency
      7. 8.3.7  Safe Start-Up into Prebiased Outputs
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Enable and Adjust UVLO
      11. 8.3.11 Adjustable Switching Frequency and Synchronization (SYNC)
      12. 8.3.12 Slow Start (SS/TR)
      13. 8.3.13 Power Good (PWRGD)
      14. 8.3.14 Bootstrap Voltage (BOOT) and Low Dropout Operation
      15. 8.3.15 Sequencing (SS/TR)
      16. 8.3.16 Output Overvoltage Protection (OVP)
      17. 8.3.17 Overcurrent Protection
        1. 8.3.17.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.17.2 Low-Side MOSFET Overcurrent Protection
      18. 8.3.18 TPS50601-SP Thermal Shutdown
      19. 8.3.19 Turn-On Behavior
      20. 8.3.20 Small Signal Model for Loop Response
      21. 8.3.21 Simple Small Signal Model for Peak Current Mode Control
      22. 8.3.22 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
      2. 8.4.2 Continuous Current Mode (CCM) Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Operating Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Slow Start Capacitor Selection
        6. 9.2.2.6 Bootstrap Capacitor Selection
        7. 9.2.2.7 Undervoltage Lockout (UVLO) Set Point
        8. 9.2.2.8 Output Voltage Feedback Resistor Selection
          1. 9.2.2.8.1 Minimum Output Voltage
        9. 9.2.2.9 Compensation Component Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Device Nomenclature

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN –0.3 7 V
PVIN –0.3 7
EN –0.3 5.5
BOOT –0.3 14
VSENSE –0.3 3.3
COMP –0.3 3.3
PWRGD –0.3 5.5
SS/TR –0.3 5.5
SYNC –0.3 7
Output voltage BOOT-PH 0 7 V
PH –1 7
PH 10-ns transient –3 7
Vdiff (GND to exposed thermal pad) –0.2 0.2 V
Output current 6 A
Source current PH Current limit A
RT ±100 µA
Sink current PH Current limit A
PVIN Current limit A
COMP ±200 µA
PWRGD –0.1 5 mA
Operating junction temperature –55 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TJ Junction operating temperature range –55 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS50601-SP UNIT
HKH (CFP)
20 PINS
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.514 °C/W
(1) Taken per Mil Standard 883 method 1012.1

7.5 Electrical Characteristics

TJ = –55°C to 125°C, VIN = 3 V to 6.3 V, PVIN = 1.6 V to 6.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage 1.6 6.3 V
VIN operating input voltage 3 6.3 V
VIN internal UVLO threshold VIN rising 2.75 3 V
VIN internal UVLO hysteresis 50 mV
VIN shutdown supply current VEN = 0 V 2.5 5.9 mA
VIN operating – non switching supply current VSENSE = VBG 5 10 mA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.13 1.18 V
Falling 1.05 1.09
Input current VEN = 1.1 V 3.2 μA
Hysteresis current VEN = 1.3 V 3 μA
VOLTAGE REFERENCE
Voltage reference 0 A ≤ Iout ≤ 6 A –55°C 0.767 0.795 0.804 V
25°C 0.785 0.795 0.804
125°C 0.785 0.795 0.815
MOSFET
High-side switch resistance BOOT-PH = 2.2 V 55 mΩ
High-side switch resistance(1) BOOT-PH = 6.3 V 50 mΩ
Low-side switch resistance(1) VIN = 6.3 V 50 mΩ
ERROR AMPLIFIER
Error amplifier transconductance (gm)(2) –2 μA < ICOMP < 2 μA, V(COMP) = 1 V 1300 μS
Error amplifier dc gain(2) VSENSE = 0.792 V 39000 V/V
Error amplifier source/sink(2) V(COMP) = 1 V, 40-mV input overdrive ±125 μA
Start switching threshold(2) 0.25 V
COMP to Iswitch gm(2) 18 A/V
CURRENT LIMIT
High-side switch current limit threshold (3) VIN = 6.3 V 8 11 A
Low-side switch sourcing current limit(3) VIN = 6.3 V 7 10 A
Low-side switch sinking current limit VIN = 6.3 V 3 A
THERMAL SHUTDOWN
Thermal shutdown 175 °C
Thermal shutdown hysteresis 10 °C
INTERNAL SWITCHING FREQUENCY
Internally set frequency RT = Open 395 500 585 kHz
Externally set frequency RT = 100 kΩ (1%) 480 kHz
RT = 485 kΩ (1%) 100
RT = 47 kΩ (1%) 1000
EXTERNAL SYNCHRONIZATION
SYNC out low-to-high rise time (10%/90%) Cload = 25 pF 25 111 ns
SYNC out high-to-low fall time (90%/10%) Cload = 25 pF 3 15 ns
Falling edge delay time(5) 180 °
SYNC out high level threshold IOH = 50 µA 2 V
SYNC out low level threshold IOL = 50 µA 600 mV
SYNC in low level threshold 800 mV
SYNC in high level threshold 1.85 V
SYNC in frequency range(4) Percent of program frequency –5% 5%
100 1000 kHz
PH (PH PIN)
Minimum on time Measured at 10% to 90% of VIN,
25°C, IPH = 2 A		 94 175 ns
Minimum off time BOOT-PH ≥ 3 V 500 ns
BOOT (BOOT PIN)
BOOT-PH UVLO 2.2 3 V
SLOW START AND TRACKING (SS/TR PIN)
SS charge current 2.5 μA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 30 90 mV
POWER GOOD (PWRGD PIN)
VSENSE threshold VSENSE falling (fault) 91 % Vref
VSENSE rising (good) 94 % Vref
VSENSE rising (fault) 109 % Vref
VSENSE falling (good) 106 % Vref
Output high leakage VSENSE = Vref, V(PWRGD) = 5 V 30 181 nA
Output low I(PWRGD) = 2 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 0.6 1 V
Minimum SS/TR voltage for PWRGD 1.4 V
(1) Measured at pins
(2) Ensured by design only. Not tested in production.
(3) Parameter is not tested in production.
(4) Parameter is production tested at nominal voltage with VIN = PVIN = 5V.
(5) Bench verified. Not tested in production.

7.6 Dissipation Ratings

See (1)(2)(3)(4)
PACKAGE RθJA THERMAL IMPEDANCE,
JUNCTION TO AMBIENT		 RθJC THERMAL IMPEDANCE,
JUNCTION TO CASE (THERMAL PAD)		 RθJB THERMAL IMPEDANCE,
JUNCTION TO BOARD
HKH 39.9°C/W 0.52°C/W 43.1°C/W
(1) Maximum power dissipation may be limited by overcurrent protection
(2) Power rating at a specific ambient temperature, TA, should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See power dissipation estimate in Application and Implementation for more information.
(3) Test board conditions:
  1. 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
  2. 2-oz. copper traces located on the top of the PCB
  3. 2-oz. copper ground planes on the 2 internal layers and bottom layer
  4. 40.010-inch thermal vias located under the device package
(4) For information on thermal characteristics, see SPRA953.
TPS50601-SP op_life_601_lvsa94.gif
A. See data sheet for absolute maximum and minimum recommended operating conditions.
B. Product operating life design goal is >15 years for 65°C ≤ TJ ≤ 95°C based on silicon technology characterization per MIL-PRF-38535.
C. The predicted operating lifetime versus junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 1. 6-A Continuous Current Estimated Device Life

7.7 Typical Characteristics

TPS50601-SP current_sharing_vs_load_lvsa94.gif
Figure 2. Current Sharing vs Load Current
TPS50601-SP C004_SLVSD45.png
Figure 4. Oscillator Frequency vs Temperature
TPS50601-SP C006_SLVSD45.png
Figure 6. EN Pin Hysteresis Current vs Temperature
TPS50601-SP C008_SLVSD45.png
Figure 8. EN Pin UVLO Threshold vs Temperature
TPS50601-SP C010_SLVSD45.png
Figure 10. Slow Start Charge Current vs Temperature
TPS50601-SP C012_SLVSD45.png
Figure 12. High-Side Current Limit Threshold vs Temperature
TPS50601-SP C001_SLVSD45.png
Figure 14. High-Side RDS(On) vs Temperature
TPS50601-SP C014_SLVSD45.png
Figure 16. Minimum Controllable Duty Ratio vs Temperature
TPS50601-SP C003_SLVSD45.png
Figure 3. Voltage Reference vs Temperature
TPS50601-SP C005_SLVSD45.png
Figure 5. Shutdown Quiescent Current vs Temperature
TPS50601-SP C007_SLVSD45.png
Figure 7. EN Pin Pullup Current vs Temperature
TPS50601-SP C009_SLVSD45.png
Figure 9. Non-Switching Operating Quiescent Current (VIN) vs Temperature
TPS50601-SP C011_SLVSD45.png
Figure 11. (SS-VSENSE) Offset vs Temperature
TPS50601-SP C002_SLVSD45.png
Figure 13. Low-Side RDS(On) vs Temperature
TPS50601-SP C013_SLVSD45.png
Figure 15. Minimum Controllable On-Time vs Temperature