SLUSCA7A November   2015  – July 2022 TPS51216-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDDQ Switch Mode Power Supply Control
      2. 8.3.2 VREF and REFIN, VDDQ Output Voltage
      3. 8.3.3 Soft-Start and Powergood
      4. 8.3.4 Power State Control
      5. 8.3.5 Discharge Control
      6. 8.3.6 VTT Overcurrent Protection
      7. 8.3.7 V5IN Undervoltage Lockout (UVLO) Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Pin Configuration
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 D-CAP Mode
      2. 9.1.2 Light-Load Operation
      3. 9.1.3 VTT and VTTREF
      4. 9.1.4 VDDQ Overvoltage and Undervoltage Protection
      5. 9.1.5 VDDQ Overcurrent Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 List of Materials
        2. 9.2.2.2 External Components Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 External Components Selection

The external components selection is simple in D-CAP mode.

  1. Determine the value of R4 and R5.

    The output voltage is determined by the value of the voltage-divider resistor, R4 and R5, as shown in Figure 9-4. R4 is connected between VREF and REFIN pins, and R5 is connected between the REFIN pin and GND. Setting R4 as 10-kΩ is a good starting point. Determine R5 using Equation 7.

    Equation 7. GUID-D3E98B38-DC9F-46D8-B14E-AA11F2D2A76F-low.gif
  2. Choose the inductor.

    The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum output current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio and helps stable operation.

    Equation 8. GUID-F2AE05D5-1B85-4EC2-A764-ABDA69DE362D-low.gif

    The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated in Equation 9.

    Equation 9. GUID-EB0DE604-E10A-4732-B36E-567734D867EC-low.gif
  3. Choose the OCL setting resistance, RTRIP.

    Combining Equation 4 and Equation 5, RTRIP can be obtained using Equation 10.

    Equation 10. GUID-D27C5DF3-02CC-4A9B-9569-99647E85B31C-low.gif
  4. Choose the output capacitors.

    TI recommends organic semiconductor capacitors or specialty polymer capacitors. Determine ESR to meet small signal stability and recommended ripple voltage. A quick reference is shown in Equation 11 and Equation 12.

    Equation 11. GUID-D9250AD9-D3F2-41A3-B9FD-F1633C1909E3-low.gif
    Equation 12. GUID-B7EC8AE5-50E4-477C-A238-34B45A576B62-low.gif