SLUSCA7A November   2015  – July 2022 TPS51216-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDDQ Switch Mode Power Supply Control
      2. 8.3.2 VREF and REFIN, VDDQ Output Voltage
      3. 8.3.3 Soft-Start and Powergood
      4. 8.3.4 Power State Control
      5. 8.3.5 Discharge Control
      6. 8.3.6 VTT Overcurrent Protection
      7. 8.3.7 V5IN Undervoltage Lockout (UVLO) Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Pin Configuration
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 D-CAP Mode
      2. 9.1.2 Light-Load Operation
      3. 9.1.3 VTT and VTTREF
      4. 9.1.4 VDDQ Overvoltage and Undervoltage Protection
      5. 9.1.5 VDDQ Overcurrent Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 List of Materials
        2. 9.2.2.2 External Components Selection
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.3 VTT and VTTREF

TPS51216-EP integrates two high performance, low-dropout linear regulators, VTT and VTTREF, to provide complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-μF (or larger) ceramic capacitor must be connected close to the VTTREF terminal for stable operation. The VTT responds quickly to track VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-μF (or larger) ceramic capacitor must be connected close to the VTT terminal for stable operation. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of the VTT output capacitors as a separate trace from the high-current line to the VTT pin. (Refer to Section 11.1 for details.)

When VTT is not required in the design, the following treatments are strongly recommended.

  • Connect VLDOIN to VDDQ.
  • Tie VTTSNS to VTT, and remove capacitors from VTT to float.
  • Connect VTTGND to GND.
  • Select MODE 0 or MODE 1 shown in Table 8-2 (select non-tracking discharge mode).
  • Maintain a 0.22-µF capacitor connected at VTTREF.
  • Pull down S3 to GND with 1-kΩ resistance.
GUID-E1D93FC3-A191-41D1-8711-DCAC97CA28A7-low.gifFigure 9-3 Application Circuit When VTT is not Required