SLVS845G March 2009 – August 2014 TPS54362-Q1
PRODUCTION DATA.
This section is a starting point, with theoretical representation of the values used for the application. Improving the performance of the device may require further optimization of the component values.
For this design example, use the parameters listed in Table 3.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage, V_{I} | 8 V to 28 V |
Output voltage, V_{O} | 5 V ± 2% |
Maximum output current, I_{O-max} | 3 A |
Transient response 0.25-A to 2.25-A load step | ΔV_{O} = 5% |
Reset threshold | 92% of output voltage |
Overvoltage threshold | 106% of output voltage |
Undervoltage threshold | 95% of output voltage |
The user selects the switching frequency based on the minimum on-time of the internal power switch, the maximum input voltage, the minimum output voltage, and the frequency-shift limitations. Use Equation 19 to find the maximum frequency for the regulator. Determine the value of the resistor to connect to the RT pin to set this frequency from Figure 13.
where
Because the oscillator can vary 10%, decrease the frequency by 10%. Further, to keep the switching frequency outside the AM band, one can select f_{(sw)} as 400 kHz (500 kHz in the application example).
Calculate the minimum inductor value using Equation 21.
k_{(IND)} is the coefficient that represents the amount of inductor ripple current relative to the maximum output current. Calculate the ripple using Equation 20.
The output capacitor filters the inductor ripple current, and so the typical range of this ripple current is in the range calculated with k_{(IND)} = 0.2 to 0.3, depending on the ESR and the ripple-current rating of the output capacitor. The minimum inductor value calculated is 14.5 μH; choose an inductor ≈ 22 μH.
where
Calculate inductor L_{(O)}:
where
The RMS (root-mean-square) and peak current flowing in the inductor is:
Inductor peak current:
The selection of the output capacitor determines several parameters in the operation of the converter, the modulator pole, voltage droop on the output capacitor, and the output ripple.
During a load step from no load to full load or changes in the input voltage, the output capacitor must hold up the output voltage above a certain level for a specified time and not issue a reset, until the main regulator control loop responds to the change. Equation 25 determines the minimum output capacitance required to allow sufficient droop on the output voltage without issuing a reset.
The capacitance value determines the modulator pole and the rolloff frequency due to the LC output filter double pole – Equation 9.
The output ripple voltage is a product of the output capacitor ESR and ripple current – Equation 27.
Using Equation 24, the minimum capacitance needed to maintain the desired output voltage during a high-to-low load transition and prevent overshoot is 157 μF.
where
The calculation of minimum capacitance needed for transient load response, using Equation 25, yields 53 μF.
The calculation of minimum capacitance needed for output voltage ripple specification, using Equation 26, yields 1.18 μF.
The most critical condition based on the foregoing calculations indicates that the output capacitance must be a minimum of 157 μF to keep the output voltage in regulation during load transients.
Factoring in additional capacitance de-ratings for temperature, aging, and dc bias yields a value of 220 μF. Equation 27 calculates the ESR required to meet the ripple-voltage tolerance of the system, but for system stability the ESR should not exceed 100 mΩ.
Maximum ESR of the out capacitor based on output ripple voltage specification is:
Output capacitor root-mean-square (rms) ripple current. This is to prevent excess heating or failure due to high ripple currents. This parameter is sometimes specified by the manufacturers.
The TPS54362-Q1 device requires an external Schottky diode connected between the PH pin and the power ground termination. The absolute voltage at the PH pin should not go beyond the values mentioned in Absolute Maximum Ratings. The Schottky diode conducts the output current during the off state of the internal power switch. This Schottky diode must have a reverse breakdown higher than the maximum input voltage of the application. The low forward voltage of a Schottky diode makes it ideal for this situation. Select the Schottky diode based on the appropriate power rating, which factors in the dc conduction losses and the ac losses due to the high switching frequencies; Equation 29 determines the power requirement.
where
The recommended part numbers of the Flyback Schottky diodes are PDS360 and SBR8U60P5.
The requires an input ceramic decoupling capacitor with type X5R or X7R dielectric, and bulk capacitance to minimize input ripple voltage. The dc voltage rating of this input capacitance must be greater than the maximum input voltage. The capacitor must have an input ripple current rating higher than the maximum input ripple current of the converter for the application; Equation 30 determines the ripple current.
The input capacitors for power regulators are chosen to have reasonable capacitance-to-volume ratio and fairly stable over temperature. The value of the input capacitance also determines the input ripple voltage of the regulator, shown by Equation 31.
In the design example, the R4 selection is 187 kΩ; using Equation 1, R4 calculates as 35.7 kΩ. To minimize the effect of leakage current on the VSENSE pin, the current flowing through the feedback network should be greater than 5 μA in order to maintain output accuracy. Higher resistor values help improve the converter efficiency at low output currents, but may introduce noise immunity problems.
Use Equation 6to determine the value of R3 to set the overvoltage threshold at 1.06 × 5.5 V. The total resistor network from the VReg output to ground is approximately 100 kΩ (this is R1 + R2 +R3). The calculated value of R3 is then 15.09 kΩ. Use the nearest standard value, which is 15 kΩ. This pin may require a noise decoupling capacitor to ensure proper operation; the value chosen for this design is 56 pF.
Using Equation 5, calculate the value of R2 + R3, and then knowing R3 from the OV_TH setting, determine R2. The value of R2 + R3 yields 17.39 kΩ, which means R2 is approximately 2.32 kΩ. This sets the reset threshold at 0.92 × 5 V. This pin may require a noise-decoupling capacitor to ensure proper operation; the value chosen for this design is 15 pF. The value determined for R1 is 82.5 kΩ.
To obtain an approximation of the output load current at which the converter is operating in discontinuous mode, use Equation 32. The values used in the equation for minimum and maximum input voltage affect the duty cycle and the overall discontinuous-mode (DCM) load current. With a maximum input voltage of 28 V, the output load current for DCM is 165.8 mA, and for minimum input voltage of 8 V, the DCM-mode load current is 111.7 mA. These are nominal values, calculated without taking into consideration other factors like external component variations with temperature and aging.
where
Setting the undervoltage threshold above the reset threshold ensures the regulator operates within the specified tolerances during output load transients of low load to high load and during discontinuous conduction mode. Using Equation 4, determine the typical voltage threshold.
The soft-start capacitor determines the minimum time to reach the desired output voltage during a power-up cycle. This time is important when a load requires a controlled voltage-slew rate. Soft starting helps to limit the current draw from the input voltage supply line. This design requires a 4.7-nF capacitor to meet the soft-start criteria. If the buck converter starts up with output shorted to ground, the circuit requires a TPS54362-Q1 device and a minimum 150-nF C_{(SS)}.
Connect a 0.1-μF ceramic capacitor between the PH and BOOT pins for the converter to operate and regulate the desired output voltage. TI recommends using a capacitor with X5R or better-grade dielectric material, and a voltage rating on this capacitor of at least 25 V to allow for derating.
Make the two zeroes close to the double pole (LC), for example, f_{(z1)} ≈ f_{(z2)} ≈ .
Make the two poles above the crossover frequency f_{(c)},
Calculate C5 based on placing a zero at 50% to 75% of the output-filter double-pole frequency.
Calculate C8 by placing the first pole at the ESR zero frequency.
Set the second pole at 0.5 times the switching frequency, and also set the second zero at the output-filter double-pole frequency.
DC modulator gain (A_{(mod)}) = 8 / V_{(ramp)}
V_{(ramp)} = 0.8 V
A_{(mod)} (dB) = 20 log (10) = 20 dB
Output filter due to LC_{O} poles and C_{O} ESR zeros from Equation 9 and Equation 10.
f_{(LC)} = 3.4 kHz for LC_{O} = 22 µH, C_{O} = 100 µF
f_{(ESR)} = 15.9 kHz for C_{O} = 100 µF, ESR = 100 mΩ
Choose R4 = 187 kΩ.
Calculate the poles and zeros for a type III network using equations Equation 33 to Equation 38.
R5 = 35.7 kΩ (use standard value 35.7 kΩ)
R6 = 276 kΩ (use standard value 274 kΩ)
C5 = 340 pF (use standard value 330 pF)
C8 = 40.6 pF (use standard value 22 pF)
R9 = 2.57 kΩ (use standard value 2.55 kΩ)
C7 = 247 pF (use standard value 220 pF)
Calculate the poles and zeros based on these compensation values, using Equation 15 through Equation 18.
The power dissipation losses applicable for continuous-conduction-mode operation (CCM) are:
where:
V_{O} = Output voltage
V_{I} = Input voltage
I_{O} = Output current
t_{r }= FET switching rise time (maximum t_{r} = 40 ns)
t_{f} = FET switching fall time
V_{(drive)} = FET gate-drive voltage (typically V_{(drive)} = 6 V and maximum V_{(drive)} = 8 V)
f_{(sw)} = Switching frequency
For a given operating ambient temperature T_{A}
For a given maximum junction temperature T_{J-Max} = 150°C
where:
P_{T} = Total power dissipation (watts)
T_{A} = Ambient temperature in °C
T_{J} = Junction temperature in °C
T_{A(Max)} = Maximum ambient temperature in °C
T_{J(Max)} = Maximum junction temperature in °C
R_{θJA} = Thermal resistance of package in (°C/W)
Other factors not included in the preceding information which affect the overall efficiency and power losses are:
The output current rating for the regulator may require derating for ambient temperatures above 85°C. The derating value depends on the calculated worst-case power dissipation and the thermal management implementation in the application.
CH1: I_{O} | CH2: VIN | CH3: Vreg |
CH4: RST | V_{(VIN)} = 12 V | V_{(VReg)} = 5 V |
CH2: VIN | CH3: Vreg | CH4: PH (100 ms/div) |
V_{(VIN)} = 12 V | V_{(VReg)} = 5 V | CH4 = 1.905 kHz |
CH2: VIN | CH3: Vreg | CH4: PH (1 µs/div) |
V_{(VIN)} = 12 V | V_{(VReg)} = 5 V | CH4 = 519.1 kHz |
CH1: I_{O} | CH2: VIN | CH3: Vreg |
CH4: RST | V_{(VIN)} = 12 V | V_{(VReg)} = 5 V |
CH2: VIN | CH3: Vreg | CH4: PH (200 µs/div) |
V_{(VIN)} = 12 V | V_{(VReg)} = 5 V | CH4 = 45.7 kHz |
CH2: VIN | CH3: Vreg | CH4: PH (1 µs/div) |
V_{(VIN)} = 12 V | V_{(VReg)} = 5 V | CH4 = 523.5 kHz |