SLUSCD4B
March 2017 – May 2018
TPS543C20
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
8.4.1
Soft-Start Operation
8.4.2
Input and VDD Undervoltage Lockout (UVLO) Protection
8.4.3
Power Good and Enable
8.4.4
Voltage Reference
8.4.5
Prebiased Output Start-up
8.4.6
Internal Ramp Generator
8.4.6.1
Ramp Selections
8.4.7
Switching Frequency
8.4.8
Clock Sync Point Selection
8.4.9
Synchronization and Stackable Configuration
8.4.10
Dual-Phase Stackable Configurations
8.4.10.1
Configuration 1: Master Sync Out Clock-to-Slave
8.4.10.2
Configuration 2: Master and Slave Sync to External System Clock
8.4.11
Operation Mode
8.4.12
API/BODY Brake
8.4.13
Sense and Overcurrent Protection
8.4.13.1
Low-Side MOSFET Overcurrent Protection
8.4.13.2
High-Side MOSFET Overcurrent Protection
8.4.14
Output Overvoltage and Undervoltage Protection
8.4.15
Overtemperature Protection
8.4.16
RSP/RSN Remote Sense Function
8.4.17
Current Sharing
8.4.18
Loss of Synchronization
9
Application and Implementation
9.1
Application Information
9.2
Typical Application: TPS543C20 Stand-alone Device
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Custom Design With WEBENCH® Tools
9.2.2.2
Switching Frequency Selection
9.2.2.3
Inductor Selection
9.2.2.4
Input Capacitor Selection
9.2.2.5
Bootstrap Capacitor Selection
9.2.2.6
BP Pin
9.2.2.7
R-C Snubber and VIN Pin High-Frequency Bypass
9.2.2.8
Output Capacitor Selection
9.2.2.8.1
Response to a Load Transient
9.2.2.8.2
Ramp Selection Design to Ensure Stability
9.2.3
Application Curves
9.3
System Example
9.3.1
Two-Phase Stackable
9.3.1.1
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.3
Package Size, Efficiency and Thermal Performance
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.1.1.1
Custom Design With WEBENCH® Tools
12.1.2
Documentation Support
12.1.2.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RVF|40
MPQF268C
Thermal pad, mechanical data (Package|Pins)
RVF|40
QFND333E
Orderable Information
sluscd4b_oa
sluscd4b_pm
9.3.1.1
Application Curves
Figure 33.
Transient Response of 0.9-V Output at 12 V
IN
, Transient is 25 A to 50 A, Step is 25 A at 30 A/μs
Figure 35.
Transient Response of 50-A to 25-A Load
at 30 A/μs Fall
Figure 37.
Output Ripple and SW Node
of 0.9-V Output at 12 VIN, 0-A Output
Figure 39.
0.6-V Pre-Bias Start Up From Enable,
0.9-V Output at 12 VIN, 0-A Output
Figure 41.
Master-Slave 180° Synchronization
Figure 34.
Transient Response of 25-A to 50-A Load
at 30 A/μs Rise
Figure 36.
Output Ripple and SW Node
of 0.9-V Output at 12 V
IN
,
80
-A Output
Figure 38.
Start up from Enable,
0.9-V Output at 12 VIN,
80
-A Output
Figure 40.
Output Voltage Start-up and Shutdown,
0.9-V Output at 12 VIN, 5-A Output