SLUSCD4B March 2017 – May 2018 TPS543C20
The TPS543C20 device is a high-performance, integrated FET converter supporting current rating up to 40-A thermally. It integrates two N-channel NexFET™ power MOSFETs, enabling high power density and small PCB layout area. The drain-to-source breakdown voltage for these FETs is 20 V DC and transient. Avalanche breakdown occurs if the absolute maximum voltage rating exceeds 20 V. In order to limit the switch node ringing of the device, TI recommends adding a R-C snubber from the SW node to the PGND pins. Also a 10~100nF capacitor from VIN (Pin 25) to GND (Pin2 7) is mandatory to reduce high side FET stress. Refer to Layout Guidelines for the detailed recommendations.
The typical on-resistance (RDS(on)) for the high-side MOSFET is 3 mΩ and typical on-resistance for the low-side MOSFET is 0.9 mΩ with a nominal gate voltage (VGS) of 5 V.