SLUSCD4B March   2017  – May 2018 TPS543C20


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1  Soft-Start Operation
      2. 8.4.2  Input and VDD Undervoltage Lockout (UVLO) Protection
      3. 8.4.3  Power Good and Enable
      4. 8.4.4  Voltage Reference
      5. 8.4.5  Prebiased Output Start-up
      6. 8.4.6  Internal Ramp Generator
        1. Ramp Selections
      7. 8.4.7  Switching Frequency
      8. 8.4.8  Clock Sync Point Selection
      9. 8.4.9  Synchronization and Stackable Configuration
      10. 8.4.10 Dual-Phase Stackable Configurations
        1. Configuration 1: Master Sync Out Clock-to-Slave
        2. Configuration 2: Master and Slave Sync to External System Clock
      11. 8.4.11 Operation Mode
      12. 8.4.12 API/BODY Brake
      13. 8.4.13 Sense and Overcurrent Protection
        1. Low-Side MOSFET Overcurrent Protection
        2. High-Side MOSFET Overcurrent Protection
      14. 8.4.14 Output Overvoltage and Undervoltage Protection
      15. 8.4.15 Overtemperature Protection
      16. 8.4.16 RSP/RSN Remote Sense Function
      17. 8.4.17 Current Sharing
      18. 8.4.18 Loss of Synchronization
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: TPS543C20 Stand-alone Device
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Switching Frequency Selection
        3. Inductor Selection
        4. Input Capacitor Selection
        5. Bootstrap Capacitor Selection
        6. BP Pin
        7. R-C Snubber and VIN Pin High-Frequency Bypass
        8. Output Capacitor Selection
          1. Response to a Load Transient
          2. Ramp Selection Design to Ensure Stability
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 Two-Phase Stackable
        1. Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Package Size, Efficiency and Thermal Performance
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. Custom Design With WEBENCH® Tools
      2. 12.1.2 Documentation Support
        1. Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

  • It is absolutely critical that all GND pins, including AGND (pin 29), GND (pin 27), and PGND (pins 13, 14, 15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or plane. The number of thermal vias needed to support 40-A thermal operation should be as many as possible; in the EVM design orderable on the Web, a total of 23 thermal vias are used. The TPS543C20EVM-799 is available for purchase at
  • Place the power components (including input/output capacitors, output inductor, and TPS543C20 device) on one side of the PCB (solder side). At least one or two innner layers/planes should be inserted, connecting to power ground, in order to shield and isolate the small signal traces from noisy power lines.
  • Place the VIN decoupling capacitors as close to the PVIN and PGND as possible to minimize the input AC current loop. The high frequency decoupling capacitor (1 nF to 0.1 µF) should be placed next to the PVIN pin and PGND pin as close as the spacing rule allows. This helps surpressing the switch node ringing.
  • Place a 10-nF to 100-nF capacitor close to IC from Pin 25 VIN to Pin 27 GND.
  • Place VDD and BP decoupling capacitors as close to the device pins as possible. Do not use PVIN plane connection for VDD. VDD needs to be tapped off from PVIN with separate trace connection. Ensure to provide GND vias for each decoupling capacitor and make the loop as small as possible.
  • The PCB trace defined as switch node, which connects the SW pins and up-stream of the output inductor should be as short and wide as possible. In web orderable EVM design, the SW trace width is 400mil. Use separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these connections.
  • All sensitive analog traces and components such as RAMP, RSP, RSN, ILIM, MODE, VSEL and RT should be placed away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise coupling. In addition, MODE, VSEL, ILIM, RAMP and RT programming resistors should be placed near the device/pins.
  • The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion. Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit uses the RSP pin for on-time adjustment. It is critical to tie the RSP pin directly tied to VOUT (load sense point) for accurate output voltage result.
  • Use caution when routing of the SYNC, VSHARE and ISHARE traces for 2-phase configurations. The SYNC trace carries a rail-to-rail signal and should be routed away from sensitive analog signals, including the VSHARE, ISHARE, RT, and FB signals. The VSHARE and ISHARE traces should also be kept away from fast switching voltages or currents formed by the PVIN, AVIN, SW, BOOT, and BP pins.