SLVSGA9A March   2022  – August 2022 TPS55289

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC Power Supply
      2. 7.3.2  EXTVCC Power Supply
      3. 7.3.3  Operation Mode Setting
      4. 7.3.4  Input Undervoltage Lockout
      5. 7.3.5  Enable and Programmable UVLO
      6. 7.3.6  Soft Start
      7. 7.3.7  Shutdown and Load Discharge
      8. 7.3.8  Switching Frequency
      9. 7.3.9  Switching Frequency Dithering
      10. 7.3.10 Inductor Current Limit
      11. 7.3.11 Internal Charge Path
      12. 7.3.12 Output Voltage Setting
      13. 7.3.13 Output Current Monitoring and Cable Voltage Droop Compensation
      14. 7.3.14 Output Current Limit
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Output Short Circuit Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Mode
      2. 7.4.2 Power Save Mode
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Target Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multiread and Multiwrite
    6. 7.6 Register Maps
      1. 7.6.1 REF Register (Address = 0h, 1h)
      2. 7.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]
      3. 7.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]
      4. 7.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]
      5. 7.6.5 CDC Register (Address = 5h) [reset = 11100000h]
      6. 7.6.6 MODE Register (Address = 6h) [reset = 00100000h]
      7. 7.6.7 STATUS Register (Address = 7h) [reset = 00000011h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.13 Output Current Monitoring and Cable Voltage Droop Compensation

The TPS55289 outputs a voltage at the CDC pin proportional to the sensed voltage across an output current sensing resistor between the ISP pin and the ISN pin. Equation 6 shows the exact voltage at the CDC pin related to the sensed output current.

Equation 6. GUID-6EEBC2E6-84B5-4C5E-94D7-9A43454D8FD4-low.gif

To compensate the voltage droop across a cable from the output of the USB port to its powered device, the TPS55289 can lift its output voltage in proportion to the load current. There are two methods in the TPS55289 to implement the compensation: by setting internal register 05h or by placing a resistor between the CDC pin and AGND pin.

When using internal output voltage feedback, use the internal compensation setting. When using an external resistor divider at the FB/INT pin to set the output voltage, use the external compensation setting by placing a resistor at the CDC pin.

By default, the internal cable voltage droop compensation function is enabled with 0 V added to the output voltage. Write the value into the bit CDC [2:0] in register 05h to get the desired voltage compensation.

When using external output voltage feedback, external compensation is better than the internal register for its high accuracy. The output voltage rises in proportion to the current sourcing from the CDC pin through the resistor at the CDC pin. Use 100-kΩ resistance for the up resistor of the feedback resistor divider. Equation 7 shows the output voltage rise related to the sensed output current, the resistance at the CDC pin, and the up resistor of the output voltage feedback resistor divider.

Equation 7. GUID-04432446-1CB6-4A3C-B760-FF58B2818379-low.gif

where

  • RFB_UP is the up resistor of the resistor divider between the output and the FB/INT pin.
  • RCDC is the resistor at the CDC pin.

Figure 7-6 shows the output voltage rise versus the sensed output current and the resistor at the CDC pin when RFB_UP is 100 kΩ.

GUID-9090B891-F6CE-4F9E-AEC3-1D631B531DF7-low.gifFigure 7-6 Output Voltage Rise Versus Output Current