SLUSDX1A September 2020 – August 2021 TPS563211
This is an optional function configured by the MODE pin.
The device has a built-in power good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG/SS pin works as an open-drain output that requires a pullup resistor (to any voltage below 5.5 V). A pullup resistor of 10 kΩ is recommended to pull it up to a 5-V voltage. It can sink 0.8 mA of current and maintain its specified logic low level. Once the FB pin voltage is between 92% and 112% of the internal reference voltage (VREF) and after a deglitch time of 112 μs, the PG/SS is high impedance. The PG/SS pin is pulled low after a deglitch time of 48 μs when the FB pin voltage is lower than UVP or greater than OVP threshold, or in events of thermal shutdown, EN shutdown, or UVLO conditions. VIN must remain present for the PG/SS pin to stay low.
If the power-good output is not used when PG function is selected, it is recommended to tie to GND to get better thermal performance.
|LOGIC SIGNALS||PG LOGIC STATUS|
|VIN > UVLO||High||Not triggered||VOUT on target||High|
|VOUT > Target||Low|
|VOUT < Target||Low|
|2.5 V < VIN < UVLO||✕||✕||✕||Low|
|VIN < 2.5 V||✕||✕||✕||Undefined|