SLUSDX1A September 2020 – August 2021 TPS563211
After selecting the inductor, the output capacitor needs to be optimized. The LC filter used as the output filter has double pole at:
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. A high frequency zero introduced by internal circuit that reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of fp is located below the high frequency zero but close enough. The phase boost provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement, make sure that the L1·COUT_E value meets the range of L1·COUT_E value recommended in Table 8-2.
|0.76||5.36||20.0||1||3×22||60 to 160|
|1.05||15.0||20.0||1.5||2×22||60 to 160|
|1.8||40.0||20.0||2.2||2×22||50 to 200|
|2.5||31.6||10.0||3.3||2×22||50 to 200|
|3.3||45.3||10.0||3.3||2×22||50 to 200|
|5||73.2||10.0||4.7||2×22||50 to 200|
The capacitor value and ESR determines the amount of output voltage ripple. The device is intended for use with ceramic or other low-ESR capacitors. Use Equation 17 to determine the required RMS current rating for the output capacitor.
Two Murata GRM21BR61C226ME44L 22-μF, 0805, 16-V output capacitors are used for this design. From the data sheet, the estimated DC derating rate is 66.8% at room temperature with AC voltage of 0.2 V. The total output effective capacitance is approximately 29.4 μF. The value of L1·COUT_E is 97 μH×μF, which is within the recommended range.