SLVSD05F march   2016  – august 2023 TPS56C215

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation and D-CAP3 Control Mode
      2. 7.3.2  Eco-mode Control
      3. 7.3.3  4.7-V LDO
      4. 7.3.4  MODE Selection
      5. 7.3.5  Soft Start and Pre-biased Soft Start
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Power Good
      8. 7.3.8  Overcurrent Protection and Undervoltage Protection
      9. 7.3.9  Out-of-Bounds Operation
      10. 7.3.10 UVLO Protection
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation
      2. 7.4.2 Standby Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Output Voltage Set Point
          2. 8.2.2.1.2 Switching Frequency and MODE Selection
          3. 8.2.2.1.3 Inductor Selection
          4. 8.2.2.1.4 Output Capacitor Selection
          5. 8.2.2.1.5 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Marking

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-7E6B6A0D-E4F8-4C7F-B3E8-510FC2B25D16-low.gifFigure 5-1 RNN Package18-Pin VQFN
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
BOOT 1 I Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between BOOT and SW.
VIN 2,11 P Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and PGND.
PGND 3, 4, 5,
8, 9, 10		 G Power GND terminal for the controller circuit and the internal circuitry. Connect to AGND with a short trace.
SW 6, 7 O Switch node terminal. Connect the output inductor to this pin.
AGND 12 G Ground of internal analog circuitry. Connect AGND to PGND plane with a short trace.
FB 13 I Converter feedback input. Connect to the center tap of the resistor divider between output voltage and AGND.
SS 14 O Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external capacitor is connected, the converter starts up in 1 ms.
EN 15 I Enable input control, leaving this pin floating enables the converter. It can also be used to adjust the input UVLO by connecting to the center tap of the resistor divider between VIN and EN.
PGOOD 16 O Open-drain power good indicator, it is asserted low if output voltage is out of PGOOD threshold, overvoltage, or if the device is under thermal shutdown, EN shutdown or during soft start.
VREG5 17 I/O 4.7-V internal LDO output which can also be driven externally with a 5-V input. This pin supplies voltage to the internal circuitry and gate driver. Bypass this pin with a 4.7-µF capacitor.
MODE 18 I Switching frequency, current limit selection and light load operation mode selection pin. Connect this pin to a resistor divider from VREG5 and AGND for different MODE options shown in Table 7-3.