The VREG5 pin is the output of the internal 4.7-V linear regulator that creates the bias for all the internal circuitry and MOSFET gate drivers. The VREG5 pin needs to be bypassed with a 4.7-µF capacitor. An external voltage that is above the internal output voltage of the LDO can override the internal LDO, switching it to the external rail after a higher voltage is detected. This enhances the efficiency of the converter because the quiescent current now runs off this external rail instead of the input power supply. The UVLO circuit monitors the VREG5 pin voltage and disables the output when VREG5 falls below the UVLO threshold. When using an external bias on the VREG5 rail, any power-up and power-down sequencing can be applied but it is important to understand that if there is a discharge path on the VREG5 rail that can pull a current higher than the internal current limit of the LDO (ILIM5) from the VREG5, then the VREG5 LDO turns off thereby shutting down the output of TPS56C215. If such condition does not exist and if the external VREG5 rail is turned off, the VREG5 voltage switches over to the internal LDO voltage which is 4.7 V typically in a few nanoseconds. Figure 7-1 shows this transition of the VREG5 voltage from an external bias of 5.5 V to the internal LDO output of 4.7 V when the external bias to VREG5 is disabled while the output of TPS56C215 remains unchanged.

Figure 7-1 VREG5 Transition