SLUSDL4 February   2020 TPS59632-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  Current Sensing
      3. 7.3.3  Load-line (Droop)
      4. 7.3.4  Load Transients
      5. 7.3.5  Overshoot Reduction (OSR)
      6. 7.3.6  Undershoot Reduction (USR)
      7. 7.3.7  Autobalance Current Sharing
      8. 7.3.8  PWM And SKIP Signals
      9. 7.3.9  Bias Power (V5A, VDD, And VINTF) UVLO
      10. 7.3.10 Start-Up Sequence
      11. 7.3.11 Power Good Operation
      12. 7.3.12 Analog Current Monitor, IMON, And Corresponding Digital Output Current
      13. 7.3.13 Fault Behavior
      14. 7.3.14 Output Under Voltage Protection (UVP)
      15. 7.3.15 Output Over Voltage Protection (OVP)
      16. 7.3.16 Over Current Protection (OCP)
      17. 7.3.17 Over Current Warning
      18. 7.3.18 Input Voltage Limits
      19. 7.3.19 VID Table
    4. 7.4 User Selections
    5. 7.5 I2C Interface Operation
      1. 7.5.1 Key For Protocol Examples
      2. 7.5.2 Protocol Examples
    6. 7.6 I2C Register Maps
      1. 7.6.1 Voltage Select Register (VSR) (Address = 00h)
      2. 7.6.2 IMON Register (Address = 03h)
      3. 7.6.3 VMAX Register (Address = 04h)
      4. 7.6.4 Power State Register (Address = 06h)
      5. 7.6.5 Slew Register (Address = 07h)
      6. 7.6.6 Lot Code Registers (Address = 10-13h)
      7. 7.6.7 Fault Register (Address = 14h)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 3-Phase D-CAP+™, Step-Down Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Step 1: Select Switching Frequency
          2. 8.2.1.2.2  Step 2: Set The Slew Rate
          3. 8.2.1.2.3  Step 3: Set The I2C Address
          4. 8.2.1.2.4  Step 4: Determine Inductor Value And Choose Inductor
          5. 8.2.1.2.5  Step 5: Current Sensing Resistance
          6. 8.2.1.2.6  Step 6: Select Over Current Protection (OCP) Setting
          7. 8.2.1.2.7  Step 7: Current Monitor (IMON) Setting
          8. 8.2.1.2.8  Step 8: Set the Load-Line Slope
          9. 8.2.1.2.9  Step 9: Voltage Feedback Resistor Calculation
          10. 8.2.1.2.10 Step 10: Ramp Compensation Selection
          11. 8.2.1.2.11 Step 11 Overshoot Reduction (OSR) selection
          12. 8.2.1.2.12 Step 12: Undershoot Reduction (USR) selection
          13. 8.2.1.2.13 Step 13: Loop Compensation
        3. 8.2.1.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1  Layout Guidelines
    2. 10.2  Layout Example
    3. 10.3  Current Sensing Lines
    4. 10.4  Feedback Voltage Sensing Lines
    5. 10.5  PWM And SKIP Lines
    6. 10.6  Power Chain Symmetry
    7. 10.7  Component Location
    8. 10.8  Grounding Recommendations
    9. 10.9  Decoupling Recommendations
    10. 10.10 Conductor Widths
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C to 125°C
    • Human body model ESD classification level H2
    • Charged device model ESD classification level C3B
  • Selectable phase count: 3, 2, or 1
  • 2.5-V to 24-V conversion voltage range (Phase count, switching frequency and maximum output voltage limitations apply)
  • 7-Bit DAC voltage range: 0.50 V to 1.52 V
  • Pre-set boot with DAC voltage of 0.800 V
  • Accurate, adjustable DC load line (droop) or zero slope load-line
  • D-CAP+™ control for fast transient response
  • Patented AutoBalance™ phase balancing
  • 8 Switching frequency settings from 300 kHz to 1 MHz
  • 8 independent levels of Output voltage overshoot reduction (OSR) and undershoot reduction (USR)
  • Selectable 8-level current limit
  • Load current monitor (Analog and Digital)
  • Selectable 8-level voltage slew rate
  • Optimized efficiency at light and heavy loads
  • I2C interface for VID control, phase management and telemetry with 8 device addresses
  • 5-mm x 5-mm, 32-Pin, 0.5-mm pitch QFN power-pad package with wettable flanks