SLUSDL4 February 2020 TPS59632-Q1
PRODUCTION DATA
The functional block diagram and Figure 7-1 shows how the converter operates in CCM.
Starting with the condition that the high-side FETs are off and the low-side FETs are on, the summed current feedback (ISUM) is higher than the error amplifier output (VDROOP). ISUM falls until it hits VDROOP, which contains a component of the output ripple voltage. The PWM comparator senses where the two waveforms cross and triggers the on-time generator, which generates the internal SW_CLK signal. Each SW_CLK signal corresponds to one switching ON pulse for one phase.
During single-phase operation, every SW_CLK signal generates a switching pulse on the same phase. Also, ISUM voltage corresponds to a single-phase inductor current only.
During multi-phase operation, the controller distributes the SW_CLK signal to each of the phases in a cycle. Using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives the required interleaving of 360 / n, where n is the number of phases.