SLVS577E March   2007  – December 2014 TPS61200 , TPS61201 , TPS61202


  1. Features
  2. Applications
  3. Description
  4. Typical Application
  5. Revision History
  6. Device Options
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Controller Circuit
        1. Synchronous Operation
        2. Down Regulation
        3. Device Enable
        4. Softstart and Short-Circuit Protection
        5. Current Limit
        6. Undervoltage Lockout
        7. Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Power Save Mode
      2. 10.4.2 Down Conversion Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. Programming the Output Voltage
        2. Programming the UVLO Threshold Voltage
        3. Inductor Selection
        4. Capacitor Selection
          1. Input Capacitor
          2. Output Capacitor
          3. Capacitor at VAUX
      3. 11.2.3 Application Curves
    3. 11.3 System Examples
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Related Links
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Layout

13.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input and output capacitor, as well as the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.

The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the control ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. See Figure 29 for the recommended layout.

13.2 Layout Example

hpa179a_pcb_lvs577.gifFigure 29. EVM Layout

13.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below.

  • Improving the power dissipation capability of the PCB design
  • Improving the thermal coupling of the component to the PCB
  • Introducing airflow in the system

The maximum recommended junction temperature (TJ) of the TPS6120x devices is 125°C. The thermal resistance of the 10-pin SON 3 × 3 package (DRC) is RθJA = 41.2 °C/W, when the exposed thermal pad is soldered. Specified regulator operation is assured to a maximum ambient temperature, TA, of 85°C. Therefore, the maximum power dissipation is about 971 mW. More power can be dissipated if the maximum ambient temperature of the application is lower.

Equation 6. Q_PDmax_lvs577.gif