SLVSH51 july   2023 TPS631012 , TPS631013

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Rating
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics 
    6. 7.6 Timing Requirements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable and Soft Start
      3. 8.3.3 Device Enable (EN)
      4. 8.3.4 Output Voltage Control
      5. 8.3.5 Mode Selection (PFM/FPWM)
      6. 8.3.6 Output Discharge
      7. 8.3.7 Reverse Current Operation
      8. 8.3.8 Protection Features
        1. 8.3.8.1 Input Overvoltage Protection
        2. 8.3.8.2 Output Overvoltage Protection
        3. 8.3.8.3 Short Circuit Protection/Hiccup
        4. 8.3.8.4 Thermal Shutdown
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 I2C Update Sequence
    6. 8.6 Register Map
      1. 8.6.1 Register Description
        1. 8.6.1.1 Register Map
        2. 8.6.1.2 Register CONTROL1 (Register address: 0x02; Default: 0x08)
        3. 8.6.1.3 Register VOUT (Register address: 0x03; Default: 0x5C)
        4. 8.6.1.4 Register CONTROL2 (Register address: 0x05; Default: 0x45)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Setting the Output Voltage
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Enable and Soft Start

GUID-94647470-C1F0-4AD0-AC6C-972D568F3425-low.gif Figure 8-1 Typical Soft-Start Behavior

When the input voltage is above the UVLO rising threshold and the EN pin is pulled to a voltage above 1.2 V, the TPS631012 and TPS631013 are enabled and start up after a short delay time, td(EN).

The TPS631012 and TPS631013 have two start-up mechanisms that are controlled by the FAST_RAMP_EN bit in Register CONTROL2. Figure 8-1 shows a typical start-up case (low output load, typical output capacitance).

  • When FAST_RAMP_EN = 1, the fast ramp mode is enabled. The output ramp behavior is shown as the solid line Vo in Figure 8-1
  • When FAST_RAMP_EN = 0, the fast ramp mode is disabled. The output ramp behavior is shown as the dash line Vo in Figure 8-1

When fast ramp mode is enabled, the devices control the inductor peak current to limit the inrush current and ensure the fastest possible soft start if the capacitance is chosen lower than that for which the ramp time td(RAMP) was selected. The output voltage then rises faster than the reference voltage ramp (see phase A in Figure 8-1). To avoid an output overshoot, the current clamp is deactivated when the output is close to the target voltage and follows the reference voltage ramp slew value given by the voltage ramp, which is finishing the start up (see phase B in Figure 8-1). Transition from the current clamp operation is detected using the VT+(UVP) threshold, which is typically 90% of the target output voltage. After phase B, the output voltage is well regulated to the nominal target voltage. The current waveform depends on the output load and operation mode. The current limit during start-up has two options and is controlled by the CL_RAMP_MIN bit in Register CONTROL2.

  • When CL_RAMP_MIN = 0, the typical current limit during start-up (phase A in Figure 8-1) is 500mA
  • When CL_RAMP_MIN = 1, the typical current limit during start-up (phase A in Figure 8-1) is 1000mA

When fast ramp mode is disabled, the output voltage is totally controlled by the internal reference voltage ramp slew rate. There are three bits of TD_RAMP in Register CONTROL2 to define the output voltage ramp time.

Note that if, during start-up, the current limit (IL(lim_SS)) is lower than the current required to follow the voltage ramp controlled by TD_RAMP, the current automatically increases to follow the voltage ramp.