SLVSH51 july   2023 TPS631012 , TPS631013

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Rating
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics 
    6. 7.6 Timing Requirements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable and Soft Start
      3. 8.3.3 Device Enable (EN)
      4. 8.3.4 Output Voltage Control
      5. 8.3.5 Mode Selection (PFM/FPWM)
      6. 8.3.6 Output Discharge
      7. 8.3.7 Reverse Current Operation
      8. 8.3.8 Protection Features
        1. 8.3.8.1 Input Overvoltage Protection
        2. 8.3.8.2 Output Overvoltage Protection
        3. 8.3.8.3 Short Circuit Protection/Hiccup
        4. 8.3.8.4 Thermal Shutdown
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 I2C Update Sequence
    6. 8.6 Register Map
      1. 8.6.1 Register Description
        1. 8.6.1.1 Register Map
        2. 8.6.1.2 Register CONTROL1 (Register address: 0x02; Default: 0x08)
        3. 8.6.1.3 Register VOUT (Register address: 0x03; Default: 0x5C)
        4. 8.6.1.4 Register CONTROL2 (Register address: 0x05; Default: 0x45)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Setting the Output Voltage
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

Over operating junction temperature range and recommended supply voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
I2C INTERFACE
fSCL SCL clock frequency Standard mode 0 100 kHz
Fast mode 0 400
Fast mode plus (1) 0 1000
tLOW LOW period of the SCL clock Standard mode 4.7 µs
Fast mode 1.3
Fast mode plus (1) 0.5
tHIGH HIGH period of the SCL clock Standard mode 4.0 µs
Fast mode 0.6
Fast mode plus (1) 0.26
tBUF Bus free time between a STOP and
a START condition		 Standard mode 4.7 µs
Fast mode 1.3
Fast mode plus (1) 0.5
tSU:STA Set-up time for a repeated START
condition		 Standard mode 4.7 µs
Fast mode 0.6
Fast mode plus (1) 0.26
tHD:STA Hold time (repeated) START
condition		 Standard mode 4.0 µs
Fast mode 0.6
Fast mode plus (1) 0.26
tHD:DAT Data hold time Standard mode 0 µs
Fast mode 0
Fast mode plus (1) 0
tr Rise time of both SDA and SCL
signals		 Standard mode 1000 ns
Fast mode 20 300
Fast mode plus (1) 20
tf Fall time of both SDA and SCL
signals		 Standard mode 300 ns
Fast mode 20×VDD/5.5 300
Fast mode plus (1) 20×VDD/5.5 120
tsu:STO Set-up time for STOP condition Standard mode 4.0 µs
Fast mode 0.6
Fast mode plus (1) 0.26
tVD;DAT Data valid time Standard mode 3.45 µs
Fast mode 0.9
Fast mode plus (1) 0.45
tVD;ACK Data valid acknowledge time Standard mode 3.45 µs
Fast mode 0.9
Fast mode plus (1) 0.45
Cb Capacitive load for each bus line Standard mode 400 pF
Fast mode 400
(1) Fast mode plus is compatible but not compliant with I2C standard