SLVSH51 july   2023 TPS631012 , TPS631013

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Rating
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics 
    6. 7.6 Timing Requirements
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable and Soft Start
      3. 8.3.3 Device Enable (EN)
      4. 8.3.4 Output Voltage Control
      5. 8.3.5 Mode Selection (PFM/FPWM)
      6. 8.3.6 Output Discharge
      7. 8.3.7 Reverse Current Operation
      8. 8.3.8 Protection Features
        1. 8.3.8.1 Input Overvoltage Protection
        2. 8.3.8.2 Output Overvoltage Protection
        3. 8.3.8.3 Short Circuit Protection/Hiccup
        4. 8.3.8.4 Thermal Shutdown
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 I2C Update Sequence
    6. 8.6 Register Map
      1. 8.6.1 Register Description
        1. 8.6.1.1 Register Map
        2. 8.6.1.2 Register CONTROL1 (Register address: 0x02; Default: 0x08)
        3. 8.6.1.3 Register VOUT (Register address: 0x03; Default: 0x5C)
        4. 8.6.1.4 Register CONTROL2 (Register address: 0x05; Default: 0x45)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Setting the Output Voltage
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics 

Over operating junction temperature range and recommended supply voltage range (unless otherwise noted). Typical values are at VI = 3.8 V , VO  = 3.3 V and TJ = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
ISD Shutdown current into VIN VI = 3.8 V, V(EN) = 0 V TJ = 25°C 0.5 0.9 μA
IQ Quiescent current into VIN VI = 2.2 V, VO = 3.3 V, V(EN) = 2.2 V, no switching 0.15 6.1 μA
IQ Quiescent current into VOUT VI = 2.2 V, VO = 3.3 V, V(EN) = 2.2 V, no switching 8 μA
VIT+ Positive-going UVLO threshold voltage VI rising 1.5 1.55 1.599 V
VIT– Negative-going UVLO threshold voltage VI falling 1.4 1.45 1.499 V
Vhys UVLO threshold voltage hysteresis 99   mV
VI(POR)T+ Positive-going POR threshold voltage(1) maximum of VI or VO 1.25 1.45 1.65 V
VI(POR)T- Negative-going POR threshold voltage(1) 1.22 1.43 1.6 V
I/O SIGNALS
VT+ Positive-going threshold voltage EN, SDA, SCL 0.77 0.98 1.2 V
VT- Negative-going threshold voltage EN, SDA, SCL 0.5 0.66 0.76 V
Vhys Hysteresis voltage EN, SDA, SCL 300 mV
IIH High-level input current EN, SDA, SCL V(EN) = V(SDA) = V(SCL)= 1.5 V,
no pullup resistor		 ±0.01 ±0.25 µA
IIL Low-level input current EN, SDA, SCL V(EN) = V(SDA) = V(SCL) = 0 V,
 		 ±0.01 ±0.1 µA
IIB Input bias current EN, SDA, SCL V(EN) = 5.5 V ±0.01 ±0.3 µA
POWER SWITCH
rDS(on) On-state resistance Q1 VI = 3.8 V, VO = 3.3 V,
test current = 0.2 A		 45 mΩ
Q2 50 mΩ
Q3 50 mΩ
Q4 85 mΩ
CURRENT LIMIT
IL(PEAK) Switch peak current limit (2) Q1 VO =  3.3 V  Output sourcing current 2.6 3 3.35 A
Output sinking current, VI = 3.3  V –0.7 –0.55 –0.45 A
IPFM_entry PFM mode entry threshold (peak) current (2) IO falling 145 mA
PROTECTION FEATURES
VT+(OVP) Positive-going OVP threshold
voltage		 5.55 5.75 5.95 V
VT+(IVP) Positive-going IVP threshold
voltage		 5.55 5.75 5.95 V
TSD_R Thermal shutdown threshold temperature TJ rising  160 °C
TSD_HYS Thermal shutdown hysteresis 25 °C
TIMING PARAMETERS
td(EN) Delay between a rising edge on the EN pin and the start of the output voltage ramp 0.87 1.5 ms
td(ramp) Soft-start ramp time 6.42 7.55 8.68 ms
fSW Switching frequency 1.8 2 2.2 MHz
(1) The POR (Power On Reset) threshold is the minimum supply of the internal VMAX block that allows the device to operate
(2) Current limit production test are performed under DC conditions. The current limit in operation is somewhat higher and depending on propagation delay and the applied external components