SLVSB64I November 2011 – March 2018 TPS65217
By default, all three DC/DC converters go to pulse-frequency modulation (PFM) mode at light loads, and fixed-frequency pulse-width modulation (PWM) mode at heavy loads. In some applications, forcing PWM operation even at light loads is required, which is done by setting the PFM_ENx bits in the DEFSLEW registers to 1b (default setting is 0b). In PFM mode, the converter skips switching cycles and operates with decreased frequency with a minimum quiescent current to keep high efficiency. The converter positions the output voltage typically 1% above the nominal output voltage. This voltage-positioning feature minimizes the voltage drop caused by a sudden load step.
The converters go from PWM to PFM mode after the inductor current in the low-side MOSFET switch becomes
When the converters are in power-save mode, the output voltage is monitored with a PFM comparator. As the output voltage decreases to less than the PFM comparator threshold of VOUT + 1%, the device starts a PFM current pulse. Starting the pulse is done by turning on the high-side MOSFET and ramping up the inductor current. Then the high-side MOSFET turns off and the low-side MOSFET switch turns on until the inductor current becomes 0 A again.
The converter effectively delivers a current to the output capacitor and the load. If the load is less than the delivered current, the output voltage rises. If the output voltage is equal to or greater than the PFM comparator threshold, the device stops switching and goes to a sleep mode with a typical 15-µA current consumption. In case the output voltage is still less than the PFM comparator threshold, additional PFM current pulses are generated until the PFM comparator threshold is reached. The converter starts switching again after the output voltage decreases to less than the PFM comparator threshold.
With one threshold comparator, the output-voltage ripple during PFM mode operation can be kept very small. The ripple voltage depends on the PFM comparator delay, the size of the output capacitor, and the inductor value. Increasing the value of the output capacitors, inductors, or both keeps the output ripple at a minimum.
The converter goes from PFM mode and goes to PWM mode the output current can no longer be supported in PFM mode or if the output voltage decreases to less than a second threshold, called the PFM comparator-low threshold. This PFM comparator-low threshold is set to a value of VOUT – 1% and enables a fast transition from power-save mode to PWM mode during a load step.
The power-save mode can be disabled through the I2C interface for each of the step-down converters, independently of each other. If the power-save mode is disabled, the converter then operates in fixed-PWM mode.