SLVSB64I November 2011 – March 2018 TPS65217
When the power-up sequence is initiated, STROBE1 occurs and any rail assigned to this strobe is enabled. After a delay time of DLY1, STROBE2 occurs and the rail assigned to this strobe is powered up. The sequence continues until all strobes have occurred and all DLYx times have been executed.
The default power-up sequence can be changed by writing to the SEQ1 through SEQ6 registers. Strobes are assigned to rails by writing to the SEQ1 through SEQ4 registers. A rail can be assigned to only one strobe but multiple rails can be assigned to the same strobe. Delays between strobes are defined in the SEQ5 and SEQ6 registers.
The power-up sequence is executed if the following events occurs:
From the OFF state (going to the ACTIVE state):
The PWR_EN pin is level-sensitive (opposed to edge-sensitive), and the pin can be asserted before or after the previously listed power-up events. However, the PWR_EN pin must be asserted within 5 s of the power-up event; otherwise, the power-down sequence is triggered and the device goes to the OFF state. If a fault occurs because the device is in undervoltage lockout (UVLO) or requires overtemperature shutdown (OTS), the device goes to the OFF state.
From the SLEEP state (going to the ACTIVE state):
In the SLEEP state, the power-up sequence can be triggered by asserting the PWR_EN pin only, and the push-button press or AC and USB assertion are not required. If a fault occurs because the device is in undervoltage lockout (UVLO) or requires overtemperature shutdown (OTS), the device goes to the OFF state.
In the ACTIVE state:
The sequencer can be triggered any time by setting the SEQUP bit in the SEQ6 register high. The SEQUP bit is automatically cleared after the sequencer is complete.
Rails that are not assigned to a strobe (the SEQ bit set to 0000b) are not affected by power-up and power-down sequencing and stay in their current ON or OFF state regardless of the sequencer. Any rail can be enabled or disabled at any time by setting the corresponding enable bit in the ENABLE register with the only exception that the ENABLE register cannot be accessed while the sequencer is active. Enable bits always reflect the current enable state of the rail, that is, the sequencer sets or resets the enable bits for the rails under its control. Also, whenever faults occur which shut-down the power-rails, the corresponding enable bits are reset.