SLVSB64I November 2011 – March 2018 TPS65217
The primary PGOOD pin has similar functionality to the LDO_PGOOD pin except that PGOOD monitors the DCDC1, DCDC2, and DCDC3 converters, and the LDO3 and LDO4 outputs configured as LDO regulators. The user can also choose to monitor the LDO1 and LDO2 regulators by setting the LDO1PGM and LDO2PGM mask bits low in the DEFPG register. By default, the power-good signal of the LDO1 and LDO2 regulators does not affect the PGOOD pin (mask bits are set to 1b by default). In normal operation the PGOOD pin is high in the ACTIVE state but low in the SLEEP, RESET, and OFF states.
In the SLEEP state and the WAIT PWR_EN state, the PGOOD pin is forced low. The PGOOD pin is set high after the device goes to the ACTIVE state, the power sequencer is complete, and the PGDLY time is expired.