SBVS123C December   2008  – March 2025 TPS737-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Noise
      2. 6.3.2 Internal Current Limit
      3. 6.3.3 Enable Pin and Shutdown
      4. 6.3.4 Reverse Current
      5. 6.3.5 Thermal Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Dropout Voltage
        3. 7.2.2.3 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Improve PSRR and Noise Performance
        2. 7.4.1.2 Power Dissipation
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPS737-Q1 DRB Package,8-Pin VSON(Top View) Figure 4-1 DRB Package,8-Pin VSON(Top View)
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
EN 5 I Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. See the Enable Pin and Shutdown section for more details. Do not leave EN floating. Connect EN to IN if this pin is not used.
FB 3 I Adjustable voltage version only. This pin is the input to the control loop error amplifier, and is used to set the output voltage of the device.
GND 4, Pad G Ground
IN 8 I Unregulated input supply
NR 3 — Fixed voltage versions only. Connecting an external capacitor to this pin bypasses noise generated by the internal band-gap, reducing output noise to very low levels.
OUT 1 O Regulator output. A 1µF or larger capacitor of any type is required for stability.
NC 2, 6, 7 — No internal connection