SLVS351Q September   2002  – June 2025 TPS796

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Active Discharge (New Chip)
      2. 6.3.2 Shutdown
      3. 6.3.3 Start-Up
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Regulator Protection
        1. 6.3.5.1 Current Limit
        2. 6.3.5.2 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Feed-forward Capacitor (CFF)
      4. 7.1.4 Adjustable Configuration
      5. 7.1.5 Load Transient Response
      6. 7.1.6 Dropout Voltage
        1. 7.1.6.1 Exiting Dropout
      7. 7.1.7 Noise Reduction Pin (legacy chip)
      8. 7.1.8 Power Dissipation (PD)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Best Design Practices
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
        2. 7.4.1.2 Regulator Mounting
        3. 7.4.1.3 Estimating Junction Temperature
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.4 Adjustable Configuration

The output voltage of the TPS79601 adjustable regulator is programmed using an external resistor divider, as Figure 7-1 shows.

TPS796 Typical Application, Adjustable Output Figure 7-1 Typical Application, Adjustable Output

The output voltage is calculated using Equation 2:

Equation 2. TPS796

where:

  • VREF = 1.2246 V typical (the internal reference voltage)

For the TPS796 (legacy chip), resistors R1 and R2 should be chosen for approximately 40μA divider current. Lower value resistors can be used for improved noise performance, but the device wastes more power. Higher values should be avoided, as leakage current at FB increases the output voltage error.

The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 μA, C1 = 15 pF for stability, and then calculate R1 using Equation 3:

Equation 3. TPS796

Similarly, for the TPS796 (new chip), to disregard the effect of the FB pin current error term and to achieve best accuracy, choose R2 to be equal to or smaller than 550 kΩ so that the current flowing through R1 and R2 is at least five times larger than the IFB current listed in the Electrical Characteristics table. Lowering the value of R2 increases the immunity against noise injection. Increasing the value of R2 reduces the quiescent current for achieving higher efficiency at low load currents. Equation 4 calculates the setting that provides the maximum feedback divider series resistance.

Equation 4. (R1 + R2) ≤ VOUT / (IFB × 5)