SBVS197F May   2013  – October 2015 TPS7A8300

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ANY-OUT Programmable Output Voltage
      2. 7.3.2 Adjustable Operation
      3. 7.3.3 ANY-OUT Operation
      4. 7.3.4 2-A LDO with an Internal Charge Pump
        1. 7.3.4.1 Dropout Voltage (VDO)
        2. 7.3.4.2 Output Voltage Accuracy
        3. 7.3.4.3 Internal Charge Pump
      5. 7.3.5 Low-Noise, 0.8-V Reference
      6. 7.3.6 Internal Protection Circuitry
        1. 7.3.6.1 Undervoltage Lockout (UVLO)
        2. 7.3.6.2 Internal Current Limit (I(LIM))
        3. 7.3.6.3 Thermal Protection
      7. 7.3.7 Programmable Soft-Start
      8. 7.3.8 Power-Good Function
      9. 7.3.9 Integrated Resistance Network (ANY-OUT)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with 1.1 V > VIN > 1.4 V
      2. 7.4.2 Operation with 1.4 V ≥ VIN > 6.5 V
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up
        1. 8.1.1.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 8.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 8.1.1.3 Soft-Start and Inrush Current
      2. 8.1.2 Capacitor Recommendation
        1. 8.1.2.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 8.1.2.2 Feed-Forward Capacitor (CFF)
      3. 8.1.3 AC Performance
        1. 8.1.3.1 Power-Supply Ripple Rejection (PSRR)
        2. 8.1.3.2 Load-Step Transient Response
        3. 8.1.3.3 Noise
        4. 8.1.3.4 Behavior when Transitioning from Steady Dropout into Regulation
      4. 8.1.4 Power Dissipation (PD)
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configurations and Functions

RGW Package
5-mm × 5-mm VQFN-20
Top View
TPS7A8300 po_bvs197.gif
RGR Package
3.5-mm × 3.5-mm VQFN-20
Top View
TPS7A8300 po_bvs197.gif

Pin Functions

PIN DESCRIPTION
NAME NO. I/O
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V 5, 6, 7, 9, 10, 11 I Output voltage setting pins. Connect these pins to ground or leave floating. Connecting these pins to ground increases the output voltage by the value of the pin name; multiple pins can be simultaneously connected to GND to select the desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable Output Voltage section for more details.
BIAS 12 I BIAS supply voltage pin for the use of 1.1 V ≤ VIN ≤ 1.4 V and to connect a 10-µF capacitor between this pin and ground.
EN 14 I Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device.
See the Start-Up section for more details.
FB 3 I Output voltage feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT (as close to the device as possible) is recommended for low-noise applications to maximize ac performance. The use of a feed-forward capacitor may disrupt PG (power good) functionality.
See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.
GND 8, 18 — Ground pin. These pins must be externally shorted for the RGR package option.
IN 15-17 I Input supply voltage pin. A 10-μF input ceramic capacitor is required. See the Input and Output Capacitor Requirements (CIN and COUT) section for more details.
OUT 1, 19, 20 O Regulated output pin. A 22-μF or larger ceramic capacitor is required for stability (a 10-μF minimum effective capacitance is required).
See the Input and Output Capacitor Requirements (CIN and COUT) section for more details.
PG 4 O Active-high power-good pin. An open-drain output indicates when the output voltage reaches 89% of the target. The use of a feed-forward capacitor may disrupt PG (power good) functionality.
See the Power-Good Function section for more details.
SNS 2 I Output voltage sense input pin. Connect this pin only if the ANY-OUT feature is used.
See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.
NR/SS 13 — Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft-start function. Although not required, a capacitor is recommended for low-noise applications to connect a 10-nF capacitor from NR/SS to GND (as close to the device as possible) to maximize ac performance. See the Noise-Reduction and Soft-Start Capacitor (CNR/SS) section for more details.
Thermal Pad Pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.