SNVSCE7A January   2024  – May 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4.2 REG_TMR

The REG_TMR (for regulation timer) is an adjustable time monitor that monitors the time it takes to VOUTx > VONx. The user can program the REG_TMR using a single resistor between REG_TMR and GND. The range of the resistor (RREG) is between 10.5kΩ to 1.18MΩ, for a 264μs to 23.63ms, respectively. If the user does not want the REG_TMR to be active, the pin can be left floating. In this case, VOUTx has infinite time to cross the VONx voltage. The REG_TMR is only active during the sequence up.
Note: If the REG_TMR is left floating and the VONx voltage is never crossed, the state machine will stay waiting indefinitely.

If active, the REG_TMR will monitor the time a VOUTx takes to cross the VONx voltage once the ENx signal is forced high. In the case the REG_TMR is expired and VOUTx has not crossed the VONx voltage, a reverse sequence down from the previously sequenced rail will be started as described in the State Machine section. Figure 8-8 shows the REG_TMR active during sequence up, from the time ENx is forced high (VOUTx starts rising). In this case, VOUTx always crosses VON before the timer is expired. The REG_TMR resistor can be selected using Equation 16. Figure 8-10 shows the linear trend between the REG_TMR resistor and the regulation time allowed for the rail to be in regulation (VOUTx > VONx).

Equation 16. R D L Y _ T M R ( k Ω ) = 50.05 × t D L Y _ T M R   ( m s ) - 2.369

Table 8-2 shows typical resistor values for different allowed regulation times.

Table 8-2 Typical REG_TMR Resistors
Allowed Regulation Time (ms) RREG_TMR (kΩ)
0.264 10.5
12.4 619
23.63 1180

TPS7H3014-SP RREG_TMR vs tREG_TMR Across Full Oscillator Range Figure 8-10 RREG_TMR vs tREG_TMR Across Full Oscillator Range