SNVSCE7A January   2024  – May 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over 3V ≤ VIN ≤ 14V, RDLY_TMR = 10.5kΩ, RREG_TMR = 10.5kΩ, CREFCAP = 470nF, CVLDO = 1µF, VPULL_UP1 = 3.3V, VPULL_UP2 = 3.3V, CPULL_UP1 = 1µF, CPULL_UP2 = 1µF,  over temperature range (TA= –55°C to 125°C), unless otherwise noted; includes group E radiation testing at TA = 25°C for QML RHA devices (1) (2) 
PARAMETER TEST CONDITIONS SUB-GROUP (3) MIN TYP MAX UNIT
SUPPLY VOLTAGES AND CURRENTS
IQ_IN  VIN quiescent current In Waiting to sequence up and down states with all outputs floating. See State Diagram 1, 2, 3 2.5 4 mA
UVLORISE VIN rising undervoltage lockout 1, 2, 3 2.72 2.79 2.84 V
UVLOFALL VIN falling udervoltage lockout 1, 2, 3 2.59 2.64 2.69
VLDO Internal linear regulator output voltage 5V ≤ VIN ≤ 14V 1, 2, 3 3.19 3.29 3.38 V
VIN < 3.24V 1, 2, 3 97% 99% × VIN
REFCAP Internal bandgap voltage 1, 2, 3 1.188 1.2 1.212 V
VPOR_IN Power on reset voltage (4) 1.6V ≤ VPULL_UPx ≤ 7V, VOL ≤ 320mV with IENx = –2mA 1, 2, 3 1.41 2
VPOR_PULL_UPx Power on reset voltage (5) VIN = 0V, VOL ≤ 320mV with IENx = –100µA 1, 2, 3 0.89 1.4
SENSE1 TO SENSE4, UP AND DOWN COMPARATOR INPUTS
VTH_SENSEx Threshold voltage at SENSEx  1, 2, 3 593 599 605 mV
IHYS_SENSEx SENSEx hysteresis current VSENSEx = 700mV 1, 2, 3 23.28 24 24.72 µA
ILKG_SENSEx Input leakage current at SENSEx VSENSEx = 500mV 1, 2, 3 2 100 nA
VTH_UP Rising threshold voltage at UP 1, 2, 3 580 598 615 mV
VTH_DOWN Falling threshold voltage at DOWN 1, 2, 3 483 498 512 mV
VHYS_UP_DOWN UP and DOWN hysteresis voltage 1, 2, 3 100 mV
ILKG_UP_DOWN Input leakage current at UP and DOWN VUP = VDOWN = 500mV 1, 2, 3 2 100 nA
VTURN_OFF Channel 2, 3, 4 turn off voltage 1, 2, 3 87% 89% 91% × VLDO
EN1 TO EN4, SEQ_DONE AND PWRGD PUSH PULL OUTPUTS
VOL_ENx Low-level ENx output voltage 1.6V ≤ VPULL_UP1 ≤ 7V ILOAD = –2mA 1, 2, 3 10% x VPULL_UP1
ILOAD = –10mA
1, 2, 3

 25%
VOH_ENx High-level ENx output voltage 1.6V ≤ VPULL_UP1 ≤ 7V ILOAD = 2mA 1, 2, 3 90%
ILOAD = 10mA
1, 2, 3

 70%
VOL_SEQ_DONE Low-level SEQ_DONE output voltage 1.6V ≤ VPULL_UP2 ≤ 7V ILOAD = –2mA 1, 2, 3 10% x VPULL_UP2
ILOAD = –10mA
1, 2, 3

 25%
VOH_SEQ_DONE High-level SEQ_DONE output voltage 1.6V ≤ VPULL_UP2 ≤ 7V ILOAD = 2mA 1, 2, 3 90%
ILOAD = 10mA
1, 2, 3

 70%
VOL_PWRGD Low-level PWRGD output voltage 1.6V ≤ VPULL_UP2 ≤ 7V ILOAD = –2mA 1, 2, 3 10%
ILOAD = –10mA
1, 2, 3

 25%
VOH_PWRGD High-level PWRGD output voltage 1.6V ≤ VPULL_UP2 ≤ 7V ILOAD = 2mA 1, 2, 3 90%
ILOAD = 10mA
1, 2, 3

 70%
PULL_UPxLKG PULL_UPx leakage current VPULL_UPx = 7V 1, 2, 3 48 121 µA
SRENx_RISE Enable rising output voltage slew rate 10% to 90% of VPULL_UP1,
RLOAD = 50kΩ,
CLOAD = 100pF		 1.6V ≤ VPULL_UP1 ≤ 7V 9, 10, 11 17 125 V/µs
SRSEQ_DONE_RISE SEQ_DONE rising output voltage slew rate 10% to 90% of VPULL_UP2,
RLOAD = 50kΩ,
CLOAD = 100pF		 1.6V ≤ VPULL_UP2 ≤ 7V 9, 10, 11 17 125
SRPWRGD_RISE PWRGD rising output voltage slew rate 9, 10, 11
17		 125
SRENx_FALL Enable falling output voltage slew rate 90% to 10% of VPULL_UP1,
RLOAD = 50kΩ,
CLOAD = 100pF		 1.6V ≤ VPULL_UP1 ≤ 7V 9, 10, 11 44 126
SRSEQ_DONE_FALL SEQ_DONE falling output voltage slew rate 1.6V ≤ VPULL_UP2 ≤ 7V 9, 10, 11 44 126
SRPWRGD_FALL PWRGD falling output voltage slew rate 9, 10, 11 44 126
RENx_PULL_UP EN PMOS source output resistance ILOAD = 2mA VPULL_UP1 = 1.6V 1, 2, 3 18 40 Ω
VPULL_UP1 = 7V
1, 2, 3

 7 20
RSEQ_DONE_PULL_UP SEQ_DONE PMOS source output resistance ILOAD = 2mA VPULL_UP2 = 1.6V 1, 2, 3 18 40
VPULL_UP2 = 7V
1, 2, 3

 7 20
RPWRGD_PULL_UP PWRGD PMOS source output resistance ILOAD = 2mA VPULL_UP2 = 1.6V 1, 2, 3 18 40
VPULL_UP2 = 7V
1, 2, 3

 7 20
RENx_PULL_DOWN EN NMOS sink output resistance ILOAD = –2mA, 1.6V ≤ VPULL_UP1 ≤ 7V 1, 2, 3 7 28
RSEQ_DONE_PULL_DOWN SEQ_DONE NMOS sink output resistance ILOAD = –2mA, 1.6V ≤ VPULL_UP1 ≤ 7V
1, 2, 3

 7 28
RPWRGD_PULL_DOWN PWRGD NMOS sink output resistance ILOAD = –2mA, 1.6V ≤ VPULL_UP1 ≤ 7V 1, 2, 3 7 28
FAULT OUTPUT
RFAULT_PULL_DOWN FAULT pull down resistance IFAULT = 100µA 1, 2, 3 131 512 Ω
ILKG_FAULT FAULT leakage current VFAULT = 7V 1, 2, 3 23 600 nA
THERMAL PROTECTION
TSD_ENTER Thermal shutdown enter temperature 177 ℃
TSD_EXIT Thermal shutdown exit temperature 164
DELAY AND TIME TO REGULATION TIMERS
tDLY_TMR Delay time  RDLY_TMR = 10.5kΩ  1, 2, 3 0.205 0.268 0.342 ms
RDLY_TMR = 619kΩ  1, 2, 3 10.77 12.5 14.14
RDLY_TMR = 1.18MΩ  1, 2, 3 20 23.37 27.2
tREG_TMR Time to regulation  RREG_TMR = 10.5kΩ  1, 2, 3 0.197 0.264 0.34
RREG_TMR = 619kΩ  1, 2, 3 10.8 12.4 14.1
RREG_TMR = 1.18MΩ 1, 2, 3 20.3 23.63 27.2
(1) See the 5962R23201VXC SMD (standard microcircuit drawing) for additional information on the RHA devices.
(2) All voltage values are with respect to GND.
(3) For subgroup definitions, see Quality Conformance Inspection table.
(4) VPOR_IN is the minimum VIN voltage for a controlled output state, when 1.6V ≤ VPULL_UPx ≤ 7V. Below VPOR_IN, the output cannot be determined.
(5) VPOR_PULL_UPx is the minimum VPULL_UPx voltage for a controlled output state, when VIN ≤ 3V. Below VPOR_PULL_UPx the output cannot be determined.