SNVSCE7A January   2024  – May 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

Over 3V ≤ VIN ≤ 14V, RDLY_TMR = 10.5kΩ, RREG_TMR = 10.5kΩ, CREFCAP = 470nF, CVLDO = 1µF, VPULL_UP1 = 3.3V, VPULL_UP2 = 3.3V, CPULL_UP1 = 1µF, CPULL_UP2 = 1µF, over temperature range (TA = –55°C to 125°C) unless otherwise noted; includes group E radiation testing at TA = 25°C for RHA devices (1)
PARAMETER TEST CONDITIONS SUB-GROUP (2) MIN TYP MAX UNIT
tStart_up_delay Start-up delay time (3) VREFCAP ≥ 1.1V, See Figure 7-1 4, 5, 6 2.8 ms
tpd_ENx ENx propagation delay DLY_TMR = Open, REG_TMR=Open,
VOVERDRIVE = 10mV,
VPULL_UPx=1.6V,
from 50% of IN to 50% OUT		 4, 5, 6 3.4 6.5 µs
tpd_SEQ_DONE SEQ_DONE propagation delay DLY_TMR = Open, REG_TMR=Open,
VOVERDRIVE = 10mV		 4, 5, 6 3.4 6.5
tpd_PWRGD PWRGD propagation delay DLY_TMR = Open, REG_TMR=Open,
VOVERDRIVE = 10mV		 4, 5, 6 3.4 6.5
tpd_SM_FAULT State machine fault propagation delay In Waiting to Sequence DOWN State 
from 33% of SENSE1 ↓ to 82% PWRGD ↓
See Figure 7-2 and State Diagram,		 4, 5, 6 3.4 4.3
tMIN_UP VUP rising minimum time for valid UP  DLY_TMR = Open, See Figure 7-3 4, 5, 6 0.27 0.7 µs
tMIN_DOWN VDOWN rising minimum time for valid DOWN DLY_TMR = Open, See Figure 7-4 4, 5, 6 0.42 0.9
th_VTH_RISE Rising theshold on VSENSEx hold time DLY_TMR = Open 4, 5, 6 0.84 1.6 µs
th_VTH_FALL Falling theshold on VSENSEx hold time DLY_TMR = Open 4, 5, 6 0.35 1 µs
(1) See the 5962R23201VXC SMD (standard microcircuit drawing) for additional information on the RHA devices (coming later)
(2) For subgroup definitions, see Quality Conformance Inspection table.
(3) During the power-on, VIN must be at or above VIN (MIN) for at least tStart_up_delay for all internal references to be within specification.