SLVSAZ9D June   2012  – February 2018 TPS81256

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Efficiency vs Load Current
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operation
      2. 8.3.2 Power-Save Mode
      3. 8.3.3 Current Limit Operation, Maximum Output Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Softstart, Enable
      2. 8.4.2 Load Disconnect and Reverse Current Protection
      3. 8.4.3 Undervoltage Lockout
      4. 8.4.4 Thermal Regulation
      5. 8.4.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Capacitor Selection CEXT
        2. 9.2.2.2 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Surface Mount Information
    4. 11.4 Thermal and Reliability Information
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • SIP|9
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.2 Layout Example

TPS81256 land_pad_lvsai0.gifFigure 23. Recommended Land Pattern Image and Dimensions
SOLDER PAD DEFINITIONS(1)(2)(3)(4)COPPER PAD SOLDER MASK (5)
OPENING		COPPER THICKNESSSTENCIL (6)
OPENING 		STENCIL THICKNESS
Non-solder-mask defined (NSMD) 0.30mm 0.360mm 1oz max (0.032mm) 0.34mm diameter 0.1mm thick
(1) Circuit traces from non-solder-mask defined PWB lands should be 75μm to 100μm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and affect reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application.
(3) Recommend solder paste is Type 3 or Type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less than 0.5mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.
(6) For best solder stencil performance use laser cut stencils with electro polishing. Chemically etched stencils give inferior solder paste volume control.