SLUSAN7C SEPTEMBER   2011  – April  2018 TPS84210

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application
      2.      Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Package Specifications
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Typical Characteristics (VIN = 5 V)
    7. 6.7 Typical Characteristics (VIN = 3.3 V)
  7. Functional Block Diagram
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting The Output Voltage
  9. Capacitor Recommendations For The TPS84210 Power Supply
    1. 9.1 Capacitor Technologies
      1. 9.1.1 Electrolytic, Polymer-Electrolytic Capacitors
      2. 9.1.2 Ceramic Capacitors
      3. 9.1.3 Tantalum, Polymer-Tantalum Capacitors
    2. 9.2 Input Capacitor
    3. 9.3 Output Capacitor
  10. 10Transient Response
  11. 11Application Schematics
  12. 12Power Good (PWRGD)
  13. 13Power-Up Characteristics
  14. 14Remote Sense
  15. 15Output On/Off Inhibit (INH)
  16. 16Slow Start (SS/TR)
  17. 17Overcurrent Protection
  18. 18Synchronization (CLK)
  19. 19Sequencing (SS/TR)
  20. 20Programmable Undervoltage Lockout (UVLO)
  21. 21Thermal Shutdown
  22. 22Layout Guidelines
  23. 23Layout Example
  24. 24EMI
  25. 25Device and Documentation Support
    1. 25.1 Receiving Notification of Documentation Updates
    2. 25.2 Community Resources
    3. 25.3 Trademarks
    4. 25.4 Electrostatic Discharge Caution
    5. 25.5 Glossary
  26. 26Mechanical, Packaging, and Orderable Information
    1. 26.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKG|39
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Synchronization (CLK)

An internal phase locked loop (PLL) has been implemented to allow synchronization between 500 kHz and 2 MHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a minimum pulse width of 75 ns. The maximum clock pulse width must be calculated using Equation 2. The clock signal amplitude must transition lower than 0.4 V and higher than 2.2 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 28.

Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor (RRT). When the external clock is present, the CLK mode overrides the RT mode. The device switches from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. The device will lock to the external clock frequency approximately 15 µs after a valid clock signal is present. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to a lower frequency before returning to the switching frequency set by the RT resistor.

Equation 2. TPS84210 q_clkpwmax_lusan7.gif
TPS84210 TPS84410RT_CLKSync_update.gifFigure 28. CLK/RT Configuration

The synchronization frequency must be selected based on the output voltages of the devices being synchronized. Table 7 shows the allowable frequencies for a given range of output voltages based on a resistive load. 5-V input applications requiring 1.5 A or less can synchronize to a wider frequency range. For the most efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires synchronizing three TPS84210 devices with output voltages of 1.2V@1.7A, 1.8@1.1AV and 3.3V@ 1.0A, all powered from VIN = 5V. Table 7 shows that all three output voltages can be synchronized to any frequency between 700 kHz to 1 MHz. For best efficiency, choose 700 kHz as the sychronization frequency.

Table 7. Synchronization Frequency vs Output Voltage

SYNCHRONIZATION FREQUENCY (kHz) RRT (kΩ) VIN = 5 V VIN = 3.3 V
IOUT ≤ 1.5 A IOUT > 1.5 A All IOUT
VOUT RANGE (V) VOUT RANGE (V) VOUT RANGE (V)
MIN MAX MIN MAX MIN MAX
500 open 0.8 1.4 0.8 0.8 0.8 1.1
550 3400 0.8 1.6 0.8 0.9 0.8 1.2
600 1800 0.8 1.9 0.8 1.1 0.8 2.0
650 1200 0.8 2.4 0.8 1.2 0.8 2.2
700 887 0.8 3.6 0.8 1.3 0.8 2.4
750 715 0.9 3.6 0.9 1.5 0.8 2.5
800 590 0.9 3.6 0.9 1.7 0.8 2.5
900 511 1.0 3.6 1.0 2.2 0.8 2.5
1000 348 1.2 3.6 1.2 2.5 0.8 2.5
1250 232 1.4 3.6 1.4 3.3 1.0 2.5
1500 174 1.7 3.6 1.7 3.6 1.1 2.5
1750 137 2.0 3.6 2.0 3.6 1.3 2.4
2000 113 2.3 3.6 2.3 3.6 1.5 2.3