SLUSAN7C SEPTEMBER   2011  – April  2018 TPS84210

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
      2.      Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Package Specifications
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Typical Characteristics (VIN = 5 V)
    7. 6.7 Typical Characteristics (VIN = 3.3 V)
  7. 7 Functional Block Diagram
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting The Output Voltage
  9. 9 Capacitor Recommendations For The TPS84210 Power Supply
    1. 9.1 Capacitor Technologies
      1. 9.1.1 Electrolytic, Polymer-Electrolytic Capacitors
      2. 9.1.2 Ceramic Capacitors
      3. 9.1.3 Tantalum, Polymer-Tantalum Capacitors
    2. 9.2 Input Capacitor
    3. 9.3 Output Capacitor
  10. 10Transient Response
  11. 11Application Schematics
  12. 12Power Good (PWRGD)
  13. 13Power-Up Characteristics
  14. 14Remote Sense
  15. 15Output On/Off Inhibit (INH)
  16. 16Slow Start (SS/TR)
  17. 17Overcurrent Protection
  18. 18Synchronization (CLK)
  19. 19Sequencing (SS/TR)
  20. 20Programmable Undervoltage Lockout (UVLO)
  21. 21Thermal Shutdown
  22. 22Layout Guidelines
  23. 23Layout Example
  24. 24EMI
  25. 25Device and Documentation Support
    1. 25.1 Receiving Notification of Documentation Updates
    2. 25.2 Community Resources
    3. 25.3 Trademarks
    4. 25.4 Electrostatic Discharge Caution
    5. 25.5 Glossary
  26. 26Mechanical, Packaging, and Orderable Information
    1. 26.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKG|39
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Electrical Characteristics

Over -40°C to 85°C free-air temperature, VIN = 3.3 V, VOUT = 1.8 V, IOUT = 2 A,
CIN1 = 47 µF ceramic, CIN2 = 220 µF poly-tantalum, COUT1 = 47 µF ceramic, COUT2 = 100 µF poly-tantalum (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOUT Output current TA = 85°C, natural convection 0 2 A
VIN Input voltage range Over IOUT range 2.95(1) 6 V
UVLO VIN Undervoltage lockout VIN = increasing 3.05 3.135 V
VIN = decreasing 2.5 2.75
VOUT(adj) Output voltage adjust range Over IOUT range 0.8 3.6 V
VOUT Set-point voltage tolerance TA = 25°C, IOUT = 0A ±1.0% (2)
Temperature variation -40°C ≤ TA ≤ +85°C, IOUT = 0A ±0.3%
Line regulation Over VIN range, TA = 25°C, IOUT = 0A ±0.1%
Load regulation Over IOUT range, TA = 25°C ±0.1%
Total output voltage variation Includes set-point, line, load, and temperature variation ±1.5% (2)
η Efficiency VIN = 5 V
IO = 1 A  		 VOUT = 3.3V, fSW = 1.5 MHz 95%
VOUT = 2.5V, fSW = 1.5 MHz 93%
VOUT = 1.8V, fSW = 1 MHz 92%
VOUT = 1.5V, fSW = 1 MHz 91%
VOUT = 1.2V, fSW =750 kHz 90%
VOUT = 1.0V, fSW = 650 kHz 88%
VOUT = 0.8V, fSW = 650 kHz 87%
VIN = 3.3V
IO = 1 A  		 VOUT = 1.8V, fSW = 1 MHz 93%
VOUT = 1.5V, fSW = 1 MHz 92%
VOUT = 1.2V, fSW = 750 kHz 91%
VOUT = 1.0V, fSW = 650 kHz 89%
VOUT = 0.8V, fSW = 650 kHz 87%
VOUT ripple Output voltage ripple 20-MHz bandwith 9 mVPP
ILIM Overcurrent threshold 3.5 A
Transient response 1.0 A/µs load step from 0.5A to 1.5A  Recovery time 80 µs
VOUT over/undershoot 45 mV
VINH-H Inhibit Control Inhibit High Voltage 1.25 Open (3) V
VINH-L Inhibit Low Voltage –0.3 1.0
II(stby) Input standby current INH pin to AGND 70 100 µA
Power Good PWRGD Thresholds VOUT rising Good 93%
Fault 107%
VOUT falling Fault 91%
Good 105%
PWRGD Low Voltage I(PWRGD) = 0.33 mA 0.3 V
Thermal Shutdown Shutdown Temperature 175 °C
Hysteresis 15 °C
CIN External input capacitance Ceramic 47 (5) µF
Non-ceramic 220(5)
COUT External output capacitance Ceramic 47 (6) 150 650(7) µF
Non-ceramic 100(6) 1000(7)
Equivalent series resistance (ESR) 25 mΩ
(1) The minimum VIN depends on VOUT and the switching frequency. Please refer to Table 7 for operating limits.
(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
(3) This control pin has an internal pullup. Do not place an external pull-up resistor on this pin. If this pin is left open circuit, the device operates when input power is applied. A small low-leakage MOSFET is recommended for control. See the application section for further guidance.
(4) The maximum synchronization clock pulse width is dependant on VIN, VOUT, and the synchronization frequency. See the Synchronization (CLK) section for more information.
(5) A minimum of 47µF of ceramic capacitance is required across the input for proper operation. Locate the capacitor close to the device. An additional 220µF of bulk capacitance is recommended. See Table 5 for more details.
(6) The amount of required output capacitance varies depending on the output voltage (see Table 3 ). The amount of required capacitance must include at least 47µF of ceramic capacitance. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 3 and Table 5 for more details.
(7) When using both ceramic and non-ceramic output capacitance, the combined maximum must not exceed 1200µF.