SNVS901A March   2014  – May 2014 TPS92511


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Pulse Level Modulation (PLM) Control
      2. 7.3.2  Pulse Level Modulation (PLM) Operaion Principles
      3. 7.3.3  PLM Control enable Common-Anode Low-Side Sensing (CALS)Technique to Save Wiring
      4. 7.3.4  Internal Regulator
      5. 7.3.5  Setting The Switching Frequency
      6. 7.3.6  Setting The LED Current
      7. 7.3.7  Integrated MOSFET
      8. 7.3.8  Inductor Selection
      9. 7.3.9  Integrated MOSFET Current Limit
      10. 7.3.10 PWM Dimming Control
      11. 7.3.11 Analog Dimming
      12. 7.3.12 High Voltage Buck Configuration
      13. 7.3.13 Thermal Foldback
      14. 7.3.14 EMI Consideration
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VIN < 4.5 V (minimum VIN)
      2. 7.4.2 Operation with DIM control
      3. 7.4.3 Linear Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 TPS92511 LED driver for 12 LEDs at 0.5A
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  9. Power Supply Recommendation
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Consideration
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  • The PCB layout of the TPS92511 application circuit plays an important role in optimizing the performance.
  • The external components should be placed as close to the TPS92511 as possible to minimize resistance and parasitic inductance of copper traces.
  • For example, D1 and L1 should be near the LX pin, and CVCC should be near the VCC pin, and the connecting copper traces are short and thick.
  • The exposed pad of the TPS92511, which is internally connected to the die substrate, should be connect to a ground plane, and the plane should be extended as much as possible on the same copper layer around the TPS92511.
  • Using numerous vias beneath the exposed pad to dissipate heat to another copper layer is also a good practice.

10.2 Layout Example

Fig_PCB.gifFigure 32. TPS92511 Board Layout

10.2.1 Thermal Consideration

ΨJT (shown in session 6.4 Thermal Information) is a relatively small value for package with exposed pad since most of the heat is dissipated through the exposed pad to the copper plate of the PCB (assuming optimized PCB layout), relatively little heat goes to the top of the device. The top of the device mold compound temperature is physically close to the device junction temperature.

For example, a 30W output TPS92511 end system at 95% power efficiency (can be estimated from the efficiency curves of Figure 13), power loss is 1.6W. Assuming all the heat is generated from the TPS92511 (which is true for high VLED), and assuming half of the heat generated is dissipated through the top of the device. Now ΨJT is 11 °C/W, the device junction temperature is estimated to be higher than the package’s top-surface temperature by 11 x 1.6 x 0.5 = 8.8 (°C). If the package top-surface temperature is measured to be 90 °C (for example by an IR camera), the device junction temperature is around 99 °C, which is within the 125°C maximum junction temperature requirement with margin.