The TPS929120-Q1 has two types of configuration registers. The registers address between 00h to 0Bh, 20h to 2Bh and 50h to 5Bh, have the almost same set of EEPROM mirror registers from 80h to 8Bh, A0h to ABh and C0h to CBh. These registers load the code from the corresponding EEPROM registers by the following operations:
- The TPS929120-Q1 starts from POR.
- The TPS929120-Q1 restarts from supply or LDO UVLO triggered.
- The TPS929120-Q1 enters fail-safe mode by watchdog timer timeout.
- Writing CONF_FORCEFS to 1 to force TPS929120-Q1 into fail-safe mode.
- Writing CLR_REG to 1 to reset all registers to default code.
- Writing CONF_EEPREADBACK to 1 to reload all registers from corresponding EEPROM.
For other configuration registers without corresponding EEPROM are cleared to default values by following operations:
- The TPS929120-Q1 starts from POR.
- The TPS929120-Q1 restarts from supply or LDO UVLO triggered.
- The TPS929120-Q1 enters fail-safe mode by watchdog-timer timeout.
- Writing CONF_FORCEFS to 1 to force TPS929120-Q1 into fail-safe mode.
- Writing CLR_REG to 1 to reset all registers to default code.