SLWS181K October   2005  – December 2015 TRF3761-A , TRF3761-B , TRF3761-C , TRF3761-E , TRF3761-F , TRF3761-G , TRF3761-H , TRF3761-J

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Electrical Characteristics, TRF3761-A
    6. 7.6  Electrical Characteristics,TRF3761-B
    7. 7.7  Electrical Characteristics, TRF3761-C
    8. 7.8  Electrical Characteristics, TRF3761-D
    9. 7.9  Electrical Characteristics, TRF3761-E
    10. 7.10 Electrical Characteristics, TRF3761-F
    11. 7.11 Electrical Characteristics, TRF3761-G
    12. 7.12 Electrical Characteristics, TRF3761-H
    13. 7.13 Electrical Characteristics, TRF3761-J
    14. 7.14 Timing Requirements
    15. 7.15 Typical Characteristics
      1. 7.15.1 Typical Characteristics, TRF3761-A (See )
      2. 7.15.2 Typical Characteristics, TRF3761-B (See )
      3. 7.15.3 Typical Characteristics, TRF3761-C (See )
      4. 7.15.4 Typical Characteristics, TRF3761-D (See )
      5. 7.15.5 Typical Characteristics, TRF3761-E (See )
      6. 7.15.6 Typical Characteristics, TRF3761-F (See )
      7. 7.15.7 Typical Characteristics, TRF3761-G (See )
      8. 7.15.8 Typical Characteristics, TRF3761-H (See )
      9. 7.15.9 Typical Characteristics, TRF3761-J (See )
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VCO
      2. 8.3.2  Divide by 2, by 4, and Output Buffer
      3. 8.3.3  N-Divider
        1. 8.3.3.1 Prescaler Stage
        2. 8.3.3.2 A and B Counter Stage
        3. 8.3.3.3 Reference Divider
      4. 8.3.4  Phase Frequency Detector (PFD) and Charge Pump Stage
      5. 8.3.5  Mux Out
      6. 8.3.6  Div 1/2/4
      7. 8.3.7  Serial interface
      8. 8.3.8  CHIP ENABLE
      9. 8.3.9  Buffer Power Down
      10. 8.3.10 External VCO IN
    4. 8.4 Device Functional Modes
      1. 8.4.1 Programmable Divider Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Programming Registers Definition
    6. 8.6 Register Maps
      1. 8.6.1 Register 1
      2. 8.6.2 Register 2
      3. 8.6.3 Register 3
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Loop Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Loop Filter Design Example
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Initial Calibration and Frequency Setup at Power Up
          1. 9.2.2.1.1 Register 1
          2. 9.2.2.1.2 Register 2
          3. 9.2.2.1.3 Register 3
        2. 9.2.2.2 Re-Calibration After Power Up
        3. 9.2.2.3 Synthesizing a Selected Frequency
      3. 9.2.3 Application Curve
      4. 9.2.4 Application Example for a High Performance RF Transmit Signal Chain
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Fully Integrated VCO
  • Low Phase Noise: –137dBc/Hz (at 600kHz, fVCO of 1.9GHz)
  • Low Noise Floor: –158dBc/Hz at 10MHz Offset
  • Integer-N PLL
  • Input Reference Frequency range: 10MHz to 104MHz
  • VCO Frequency Divided by 2-4 Output
  • Output Buffer Enable Pin
  • Programmable Charge Pump Current
  • Hardware and Software Power Down
  • 3-Wire Serial Interface
  • Single Supply: 4.5V to 5.25V Operation

2 Applications

  • Wireless Infrastructure
    • WCDMA, CDMA, GSM
    • Wideband Transceivers
    • Wireless Local Loop
    • RFID Transceivers
    • Clock generation
    • IF LO generation

3 Description

TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized for high performance applications. The TRF3761 includes a low-noise, voltage-controlled oscillator (VCO) and an integer-N PLL.

TRF3761 integrates divide-by 1, 2, or 4 options for a more flexible output frequency range. It is controlled through a 3-wire serial-programming-interface (SPI) interface. For power sensitive applications the TRF3761 can be powered down by the SPI interface or externally via chip_en pin 2.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TRF3761 VQFN (40) 6.00 mm x 6.00 mm
TRF3761-x
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Application Schematic

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K fp_app_lws181.gif