SLWS181K October   2005  – December 2015 TRF3761-A , TRF3761-B , TRF3761-C , TRF3761-E , TRF3761-F , TRF3761-G , TRF3761-H , TRF3761-J

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Electrical Characteristics, TRF3761-A
    6. 7.6  Electrical Characteristics,TRF3761-B
    7. 7.7  Electrical Characteristics, TRF3761-C
    8. 7.8  Electrical Characteristics, TRF3761-D
    9. 7.9  Electrical Characteristics, TRF3761-E
    10. 7.10 Electrical Characteristics, TRF3761-F
    11. 7.11 Electrical Characteristics, TRF3761-G
    12. 7.12 Electrical Characteristics, TRF3761-H
    13. 7.13 Electrical Characteristics, TRF3761-J
    14. 7.14 Timing Requirements
    15. 7.15 Typical Characteristics
      1. 7.15.1 Typical Characteristics, TRF3761-A (See )
      2. 7.15.2 Typical Characteristics, TRF3761-B (See )
      3. 7.15.3 Typical Characteristics, TRF3761-C (See )
      4. 7.15.4 Typical Characteristics, TRF3761-D (See )
      5. 7.15.5 Typical Characteristics, TRF3761-E (See )
      6. 7.15.6 Typical Characteristics, TRF3761-F (See )
      7. 7.15.7 Typical Characteristics, TRF3761-G (See )
      8. 7.15.8 Typical Characteristics, TRF3761-H (See )
      9. 7.15.9 Typical Characteristics, TRF3761-J (See )
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VCO
      2. 8.3.2  Divide by 2, by 4, and Output Buffer
      3. 8.3.3  N-Divider
        1. 8.3.3.1 Prescaler Stage
        2. 8.3.3.2 A and B Counter Stage
        3. 8.3.3.3 Reference Divider
      4. 8.3.4  Phase Frequency Detector (PFD) and Charge Pump Stage
      5. 8.3.5  Mux Out
      6. 8.3.6  Div 1/2/4
      7. 8.3.7  Serial interface
      8. 8.3.8  CHIP ENABLE
      9. 8.3.9  Buffer Power Down
      10. 8.3.10 External VCO IN
    4. 8.4 Device Functional Modes
      1. 8.4.1 Programmable Divider Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Programming Registers Definition
    6. 8.6 Register Maps
      1. 8.6.1 Register 1
      2. 8.6.2 Register 2
      3. 8.6.3 Register 3
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Loop Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Loop Filter Design Example
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Initial Calibration and Frequency Setup at Power Up
          1. 9.2.2.1.1 Register 1
          2. 9.2.2.1.2 Register 2
          3. 9.2.2.1.3 Register 3
        2. 9.2.2.2 Re-Calibration After Power Up
        3. 9.2.2.3 Synthesizing a Selected Frequency
      3. 9.2.3 Application Curve
      4. 9.2.4 Application Example for a High Performance RF Transmit Signal Chain
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range(2) –0.3 5.5 V
Digital I/O voltage range –0.3 VCC +0.3 V
TJ Operating virtual junction temperature range –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

7.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Power supply voltage 4.5 5 5.25 V
Power supply voltage ripple 940 μVpp
TA Operating free air temperature range –40 85 °C
TJ Operating virtual junction temperature range –40 150 °C

7.3 Thermal Information

THERMAL METRIC(1) TRF3761 UNIT
RHA (VQFN)
40 PINS
RθJA Junction-to-ambient thermal resistance Soldered slug, no airflow 26 °C/W
Soldered slug, 200-LFM airflow 20.1 °C/W
Soldered slug, 400-LFM airflow 17.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16.4 °C/W
RθJB Junction-to-board thermal resistance 4.7 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Electrical Characteristics

Supply voltage = VCC = 4.5 V to 5.25 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC PARAMETERS
ICC Total supply current TA = 25°C Divide by 1 output 130 mA
Divide by 2 output 140 mA
Divide by 4 output 150 mA
REFERENCE OSCILLATOR PARAMETERS
fref Reference frequency 10 104 MHz
Reference input sensitivity (REF_IN) 0.2 2.5 VPP
Reference input impedance (REF_IN) Parallel capacitance 5 6.52 pF
Parallel resistance 3913 Ω
PFD CHARGE PUMP
PFD frequency 30 MHz
Charge pump current (ICP_OUT ) SPI programmable 5.6 mA
DIGITAL INTERFACE (PD_OUTBUF, CHIP_EN, CLOCK, DATA, STROBE)
VIH High-level input voltage VCC - 2 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage 0.8VCC V
VOL Low-level output voltage 0.2VCC V
OUTPUT POWER
Single ended 0 dBm
Differential 3 dBm

7.5 Electrical Characteristics, TRF3761-A

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 1554MHz,
fO = 1554MHz		 100kHz offset –116.7 dBc/Hz
600kHz offset –136
1MHz offset -141.6
6MHz offset –156.1
10MHz offset -158.1
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 1554MHz,
fO = 777MHz		 100kHz offset -122.8 dBc/Hz
600kHz offset –142.7
1MHz offset –147.5
6MHz offset –157
10MHz offset –158.1
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 1554MHz,
fO = 388.5MHz		 100kHz offset –127.7 dBc/Hz
600kHz offset -148.4
1MHz offset -151.8
6MHz offset –156.3
10MHz offset –155.9
VCO phase noise,
Closed loop phase noise direct output(1) (2) (3) 		fVCO = 1554MHz,
fO = 1554MHz		 1kHz offset –83.4 dBc/Hz
600kHz offset –135
1MHz offset –140.2
10MHz offset –158.2
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 0.95°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 1554MHz,
fO = 777MHz		 1kHz offset –90.4 dBc/Hz
600kHz offset –141
1MHz offset –146.2
10MHz offset –158.25
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.63°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 1554MHz,
fO = 388.5MHz		 1kHz offset -95 dBc/Hz
600kHz offset –147
1MHz offset –151
10MHz offset –156
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.39°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.6 Electrical Characteristics,TRF3761-B

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 1651MHz,
fO = 1651MHz		 100kHz offset –119.34 dBc/Hz
600kHz offset –139
1MHz offset -142.1
6MHz offset –156.6
10MHz offset -158.6
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 1651MHz,
fO = 825.5 MHz		 100kHz offset -127.8 dBc/Hz
600kHz offset –146.5
1MHz offset –149
6MHz offset –156.2
10MHz offset –158.4
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 1651MHz,
fO = 412.75 MHz		 100kHz offset –127.3 dBc/Hz
600kHz offset -151.4
1MHz offset -153
6MHz offset –155.5
10MHz offset –155.9
VCO phase noise,
Closed loop phase noise direct output(1) (2) (3) 		fVCO = 1651MHz,
fO = 1651MHz		 1kHz offset –83.5 dBc/Hz
600kHz offset –138
1MHz offset –141.8
10MHz offset –158.2
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 0.85°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 1651MHz,
fO = 825.5 MHz		 1kHz offset –90.2 dBc/Hz
600kHz offset –146
1MHz offset –147.39
10MHz offset –158.25
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.53°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 1651MHz,
fO = 412.75 MHz		 1kHz offset -95.7 dBc/Hz
600kHz offset –151
1MHz offset –154
10MHz offset –156
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.33°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.7 Electrical Characteristics, TRF3761-C

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 1723MHz,
fO = 1700MHz		 100kHz offset –119.5 dBc/Hz
600kHz offset –138.8
1MHz offset -143.9
6MHz offset –155.3
10MHz offset –157.5
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 1723MHz,
fO = 861.5 MHz		 100kHz offset –126 dBc/Hz
600kHz offset –145.2
1MHz offset –149.5
6MHz offset –157.2
10MHz offset –158
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 1723MHz,
fO = 430.75 MHz		 100kHz offset –133 dBc/Hz
600kHz offset -151
1MHz offset -153.8
6MHz offset –156
10MHz offset –156.5
VCO phase noise,
Closed loop phase noise direct output(1) (2) (3) 		fVCO = 1723MHz,
fO = 1723MHz,		 1kHz offset –85 dBc/Hz
600kHz offset –138.34
1MHz offset –142.68
10MHz offset –157.3
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 0.87°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 1723MHz,
fO = 861.5 MHz		 1kHz offset –90.1 dBc/Hz
600kHz offset –145
1MHz offset –148.6
10MHz offset –158
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.53°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 1723MHz,
fO = 430.75 MHz		 1kHz offset –96.2 dBc/Hz
600kHz offset –151
1MHz offset –153
10MHz offset –156
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.33°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.8 Electrical Characteristics, TRF3761-D

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 1817MHz,
fO = 1817MHz		 100kHz offset –118 dBc/Hz
600kHz offset –138.5
1MHz offset -144
6MHz offset –156
10MHz offset –158
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 1817MHz,
fO = 908.5MHz		 100kHz offset –124.8 dBc/Hz
600kHz offset –145.2
1MHz offset –148
6MHz offset –157.8
10MHz offset –158.2
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 1817MHz,
fO = 454.25MHz		 100kHz offset –132 dBc/Hz
600kHz offset -151
1MHz offset -154
6MHz offset –157
10MHz offset –157.5
VCO phase noise,
Closed loop phase noise direct output(1) (2) (1) 		fVCO = 1817MHz,
fO = 1817MHz		 1kHz offset –85 dBc/Hz
600kHz offset –139
1MHz offset –144
10MHz offset –159
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 0.85°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 1817MHz,
fO = 908.5MHz		 1kHz offset –91 dBc/Hz
600kHz offset –146
1MHz offset –149
10MHz offset –159
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.47°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 1817MHz,
fO = 454.25MHz		 1kHz offset –97 dBc/Hz
600kHz offset –151
1MHz offset –154
10MHz offset –157
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.34°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.9 Electrical Characteristics, TRF3761-E

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 1869MHz,
fO = 1869MHz		 100kHz offset –118 dBc/Hz
600kHz offset –138
1MHz offset –142
6MHz offset –155
10MHz offset –157.3
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 1869MHz,
fO = 934.5MHz		 100kHz offset –126 dBc/Hz
600kHz offset –144
1MHz offset –149
6MHz offset –158
10MHz offset –158.2
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 1869MHz,
fO = 467.25MHz		 100kHz offset –132 dBc/Hz
600kHz offset –150
1MHz offset –154
6MHz offset -157
10MHz offset –157.3
VCO phase noise,
Closed loop phase noise direct output(1) (2) (3) 		fVCO = 1869MHz,
fO = 1869MHz		 1kHz offset –84.5 dBc/Hz
600kHz offset –140
1MHz offset –143.6
10MHz offset –157
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 0.9°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 1869MHz,
fO = 934.5MHz		 1kHz offset –90.7 dBc/Hz
600kHz offset –144
1MHz offset –148.5
10MHz offset –158
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.53°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 1869MHz,
fO = 467.25MHz		 1kHz offset –95 dBc/Hz
600kHz offset –150
1MHz offset –154
10MHz offset –157
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.35°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.10 Electrical Characteristics, TRF3761-F

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 1916MHz,
fO = 1916MHz		 100kHz offset -116 dBc/Hz
600kHz offset -137
1MHz offset -141
6MHz offset -155
10MHz offset -157
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 1916MHz,
fO = 958MHz		 100kHz offset -113 dBc/Hz
600kHz offset -136
1MHz offset -147.5
6MHz offset -155
10MHz offset -157.5
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 1916MHz,
fO = 479MHz		 100kHz offset -128 dBc/Hz
600kHz offset -148
1MHz offset -150
6MHz offset -155
10MHz offset -156
VCO phase noise,
Closed loop phase noise direct output(1) (2) (3) 		fVCO = 1916MHz,
fO = 1916MHz		 1kHz offset -82.5 dBc/Hz
600kHz offset -136.7
1MHz offset -142
10MHz offset -157
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 0.947°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 1916MHz,
fO = 958MHz		 1kHz offset -88.6 dBc/Hz
600kHz offset -142.6
1MHz offset -148.2
10MHz offset -158
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.477°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 1916MHz,
fO = 479MHz		 1kHz offset -95 dBc/Hz
600kHz offset -148
1MHz offset -152
10MHz offset -156
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.231°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.11 Electrical Characteristics, TRF3761-G

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 1989MHz,
fO = 1989MHz		 100kHz offset -115 dBc/Hz
600kHz offset -136
1MHz offset -141.2
6MHz offset -155.6
10MHz offset -159
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 1989MHz,
fO = 994.5MHz		 100kHz offset -121.3 dBc/Hz
600kHz offset -142.4
1MHz offset -141.5
6MHz offset -157.2
10MHz offset -158
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 1989MHz,
fO = 497.25MHz		 100kHz offset -128 dBc/Hz
600kHz offset -148
1MHz offset -151
6MHz offset -156.8
10MHz offset -157
VCO phase noise,
Closed loop phase noise direct output(1) (2) (3) 		fVCO = 1989MHz,
fO = 1989MHz		 1kHz offset -83 dBc/Hz
600kHz offset -136
1MHz offset -141
10MHz offset -159
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 1°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 1989MHz,
fO = 994.5MHz		 1kHz offset -88.7 dBc/Hz
600kHz offset -141.9
1MHz offset -147.5
10MHz offset -158
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.509°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 1989MHz,
fO = 497.25MHz		 1kHz offset -95 dBc/Hz
600kHz offset -147.9
1MHz offset -151.3
10MHz offset -156
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.252°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.12 Electrical Characteristics, TRF3761-H

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 2116MHz,
fO = 2116MHz		 100kHz offset –116 dBc/Hz
600kHz offset –136
1MHz offset -142
6MHz offset –154.2
10MHz offset –156
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 2116MHz,
fO = 1058		 100kHz offset –123.3 dBc/Hz
600kHz offset –143
1MHz offset –147.6
6MHz offset –157
10MHz offset –158.3
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 2116MHz,
fO = 529MHz		 100kHz offset –129.4 dBc/Hz
600kHz offset -149.8
1MHz offset -152.7
6MHz offset –157.7
10MHz offset –158
VCO phase noise,
Closed loop phase noise direct output(1) (2) (3) 		fVCO = 2116MHz,
fO = 2116MHz		 1kHz offset –84 dBc/Hz
600kHz offset –136
1MHz offset –141
10MHz offset –157
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 0.99°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 2116MHz,
fO = 1058MHz		 1kHz offset -89 dBc/Hz
600kHz offset –143
1MHz offset –148
10MHz offset –159
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.54°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 2116MHz,
fO = 529MHz		 1kHz offset –95 dBc/Hz
600kHz offset –149.5
1MHz offset –153
10MHz offset –158
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.35°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.13 Electrical Characteristics, TRF3761-J

Supply voltage = VCC = 5 V, TA = –40 to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE CHARACTERISTICS
VCO phase noise,
Free running VCO direct output		 fVCO = 2289MHz,
fO = 2289MHz		 100kHz offset –116.7 dBc/Hz
600kHz offset –135.4
1MHz offset -141
6MHz offset –153.8
10MHz offset –156.4
VCO phase noise,
Free running VCO divide-by-2 output		 fVCO = 2289MHz,
fO = 1144.5		 100kHz offset –123 dBc/Hz
600kHz offset –142
1MHz offset –147
6MHz offset –156.2
10MHz offset –157.5
VCO phase noise,
Free running VCO divide-by-4 output		 fVCO = 2289MHz,
fO = 572.25MHz		 100kHz offset –129 dBc/Hz
600kHz offset -149
1MHz offset -153
6MHz offset –157.5
10MHz offset –158
VCO phase noise,
Closed loop phase noise direct output(1) (2) (3) 		fVCO = 2289MHz,
fO = 2289MHz		 1kHz offset –83 dBc/Hz
600kHz offset –135
1MHz offset –140
10MHz offset –156
RMS phase error
Closed loop phase noise direct output(3) 		100Hz to 10MHz 1.1°
VCO phase noise,
Closed loop phase noise divide-by-2 output(1) (2) (3) 		fVCO = 2289MHz,
fO = 1144.5MHz		 1kHz offset –89 dBc/Hz
600kHz offset -141
1MHz offset –145.7
10MHz offset –158
RMS phase error
Closed loop phase noise divide-by-2 output(3) 		100Hz to 10MHz 0.59°
VCO phase noise,
Closed loop phase noise divide-by-4 output(1) (2) (3) 		fVCO = 2289MHz,
fO = 572.25MHz		 1kHz offset –95 dBc/Hz
600kHz offset –148
1MHz offset –152
10MHz offset –158.1
RMS phase error
Closed loop phase noise divide-by-4 output(3) 		100Hz to 10MHz 0.37°
VCO gain, Kv VCO free running 23 MHz/V
Reference spur(2) –80 dBc
(1) See Application Circuit Figure 87.
(2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz.
(3) Reference oscillator RMS phase error = 0.008250°, RMS jitter = 881.764 fs.

7.14 Timing Requirements

Supply voltage = VCC = 4.5 V to 5.25 V, TA = –40 to 85 °C
MIN TYP MAX UNIT
t(CLK) Clock period 50 ns
tsu1 Setup time, data 10 ns
th Hold time, data 10 ns
tw Pulse width, STROBE 20 ns
tsu2 Setup time, STROBE 10 ns
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K tim_dia_lws181.gif
A. The first 4 bits, DB(3-0), of data are Address bits. The 28 remaining bits, DB(31-4), are part of the command. The command is little endian or lower bits first.
Figure 1. Serial Programming Timing Diagram

7.15 Typical Characteristics

7.15.1 Typical Characteristics, TRF3761-A (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_cl1554_lws181.gif Figure 2. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_cl777_lws181.gif Figure 4. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_cl388_lws181.gif Figure 6. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_1_lws181.gif Figure 8. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_4_lws181.gif Figure 10. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_ol1554_lws181.gif Figure 3. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_ol777_lws181.gif Figure 5. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_ol388_lws181.gif Figure 7. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_2_lws181.gif Figure 9. Direct-By-2 Output: PFD Frequency Spurs

7.15.2 Typical Characteristics, TRF3761-B (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K b_cl1651_lws181.gif Figure 11. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K b_cl825_lws181.gif Figure 13. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K b_cl412_lws181.gif Figure 15. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_1a_lws181.gif Figure 17. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_4a_lws181.gif Figure 19. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K b_ol1651_lws181.gif Figure 12. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K b_ol825_lws181.gif Figure 14. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K b_ol412_lws181.gif Figure 16. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_2a_lws181.gif Figure 18. Divide-By-2 Output: PFD Frequency Spurs

7.15.3 Typical Characteristics, TRF3761-C (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K c_cl1723_lws181.gif Figure 20. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K c_cl861_lws181.gif Figure 22. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K c_cl430_lws181.gif Figure 24. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_1a_lws181.gif Figure 26. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_4a_lws181.gif Figure 28. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K c_ol1723_lws181.gif Figure 21. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K c_ol861_lws181.gif Figure 23. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K c_ol430_lws181.gif Figure 25. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K a_div_2a_lws181.gif Figure 27. Divide-By-2 Output: PFD Frequency Spurs

7.15.4 Typical Characteristics, TRF3761-D (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_cl1801_lws181.gif Figure 29. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_cl900_lws181.gif Figure 31. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_cl450_lws181.gif Figure 33. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_div_1_lws181.gif Figure 35. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_div_4_lws181.gif Figure 37. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_ol1801_lws181.gif Figure 30. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_ol900_lws181.gif Figure 32. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_ol450_lws181.gif Figure 34. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K d_div_2_lws181.gif Figure 36. Divide-By-2 Output: PFD Frequency Spur

7.15.5 Typical Characteristics, TRF3761-E (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_cl1869_lws181.gif Figure 38. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_cl934_lws181.gif Figure 40. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_cl467_lws181.gif Figure 42. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_div_1_lws181.gif Figure 44. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_div_4_lws181.gif Figure 46. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_ol1869_lws181.gif Figure 39. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_ol934_lws181.gif Figure 41. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_ol467_lws181.gif Figure 43. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K e_div_2_lws181.gif Figure 45. Divide-By-2 Output: PFD Frequency Spurs

7.15.6 Typical Characteristics, TRF3761-F (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_cl1916_lws181.gif Figure 47. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_cl958_lws181.gif Figure 49. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_cl479_lws181.gif Figure 51. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_div_1_lws181.gif Figure 53. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_div_4_lws181.gif Figure 55. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_ol1916_lws181.gif Figure 48. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_ol958_lws181.gif Figure 50. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_ol479_lws181.gif Figure 52. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K f_div_2_lws181.gif Figure 54. Divide-By-2 Output: PFD Frequency Spurs

7.15.7 Typical Characteristics, TRF3761-G (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_cl1989_lws181.gif Figure 56. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_cl994_lws181.gif Figure 58. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_cl497_lws181.gif Figure 60. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_div_1_lws181.gif Figure 62. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_div_4_lws181.gif Figure 64. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_ol1989_lws181.gif Figure 57. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_ol994_lws181.gif Figure 59. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_ol497_lws181.gif Figure 61. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K g_div_2_lws181.gif Figure 63. Divide-By-2 Output: PFD Frequency Spurs

7.15.8 Typical Characteristics, TRF3761-H (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_cl2100_lws181.gif Figure 65. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_cl1050_lws181.gif Figure 67. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_cl525_lws181.gif Figure 69. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_div_1_lws181.gif Figure 71. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_div_4_lws181.gif Figure 73. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_ol2100_lws181.gif Figure 66. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_ol1050_lws181.gif Figure 68. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_ol525_lws181.gif Figure 70. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K h_div_2_lws181.gif Figure 72. Divide-By-2 Output: PFD Frequency Spurs

7.15.9 Typical Characteristics, TRF3761-J (See Figure 87)

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_cl2216_lws181.gif Figure 74. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_cl1108_lws181.gif Figure 76. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_cl554_lws181.gif Figure 78. Closed Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_div_1_lws181.gif Figure 80. Direct Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_div_4_lws181.gif Figure 82. Divide-By-4 Output: PFD Frequency Spurs
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_ol2216_lws181.gif Figure 75. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_ol1108_lws181.gif Figure 77. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_ol554_lws181.gif Figure 79. Open Loop VCO Phase Noise
TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K j_div_2_lws181.gif Figure 81. Divide-By-2 Output: PFD Frequency Spurs