SLWS181K October   2005  – December 2015 TRF3761-A , TRF3761-B , TRF3761-C , TRF3761-E , TRF3761-F , TRF3761-G , TRF3761-H , TRF3761-J

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Electrical Characteristics, TRF3761-A
    6. 7.6  Electrical Characteristics,TRF3761-B
    7. 7.7  Electrical Characteristics, TRF3761-C
    8. 7.8  Electrical Characteristics, TRF3761-D
    9. 7.9  Electrical Characteristics, TRF3761-E
    10. 7.10 Electrical Characteristics, TRF3761-F
    11. 7.11 Electrical Characteristics, TRF3761-G
    12. 7.12 Electrical Characteristics, TRF3761-H
    13. 7.13 Electrical Characteristics, TRF3761-J
    14. 7.14 Timing Requirements
    15. 7.15 Typical Characteristics
      1. 7.15.1 Typical Characteristics, TRF3761-A (See )
      2. 7.15.2 Typical Characteristics, TRF3761-B (See )
      3. 7.15.3 Typical Characteristics, TRF3761-C (See )
      4. 7.15.4 Typical Characteristics, TRF3761-D (See )
      5. 7.15.5 Typical Characteristics, TRF3761-E (See )
      6. 7.15.6 Typical Characteristics, TRF3761-F (See )
      7. 7.15.7 Typical Characteristics, TRF3761-G (See )
      8. 7.15.8 Typical Characteristics, TRF3761-H (See )
      9. 7.15.9 Typical Characteristics, TRF3761-J (See )
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VCO
      2. 8.3.2  Divide by 2, by 4, and Output Buffer
      3. 8.3.3  N-Divider
        1. 8.3.3.1 Prescaler Stage
        2. 8.3.3.2 A and B Counter Stage
        3. 8.3.3.3 Reference Divider
      4. 8.3.4  Phase Frequency Detector (PFD) and Charge Pump Stage
      5. 8.3.5  Mux Out
      6. 8.3.6  Div 1/2/4
      7. 8.3.7  Serial interface
      8. 8.3.8  CHIP ENABLE
      9. 8.3.9  Buffer Power Down
      10. 8.3.10 External VCO IN
    4. 8.4 Device Functional Modes
      1. 8.4.1 Programmable Divider Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Programming Registers Definition
    6. 8.6 Register Maps
      1. 8.6.1 Register 1
      2. 8.6.2 Register 2
      3. 8.6.3 Register 3
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Loop Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Loop Filter Design Example
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Initial Calibration and Frequency Setup at Power Up
          1. 9.2.2.1.1 Register 1
          2. 9.2.2.1.2 Register 2
          3. 9.2.2.1.3 Register 3
        2. 9.2.2.2 Re-Calibration After Power Up
        3. 9.2.2.3 Synthesizing a Selected Frequency
      3. 9.2.3 Application Curve
      4. 9.2.4 Application Example for a High Performance RF Transmit Signal Chain
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

When designing the complete PLL, this section is of paramount importance in achieving the desired performance. Wherever possible, a multi-layer PCB board should be used, with at least one dedicated ground plane. A dedicated power plane (split between the supplies if necessary) is also recommended. The impedance of all RF traces (the VCO output and feedback into the PLL) should be controlled to 50Ω. All small value (10pF and 0.1µF) decoupling capacitors should be placed as close to the device pins as possible. It is also recommended that both top and bottom layers of the circuit board be flooded with ground, with plenty of ground vias dispersed as appropriate. Because the digital lines are not in use during normal operation of the device and are only used to program the device on start up and during frequency changes the analog grounds (GND) and digital grounds (DGND) are tied to the same ground plane. The most sensitive part of any PLL is the section between the charge pump output and the input to the VCO. This includes the loop filter components, and the corresponding traces. The charge pump is a precision element of the PLL and any extra leakage on its path can adversely affect performance. Extra care should be given to ensure that parasitics are minimized in the charge pump output, and that the trace runs are short and optimized. Similarly, it is also recommend that extra care is taken in ensuring that any flux residue is thoroughly cleaned and moisture baked out of the PCB. From an EMI perspective, and since the synthesizer is typically a small portion of a bigger, complex circuit board, shielding is recommended to minimize EMI effects.

11.2 Layout Example

TRF3761 TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H TRF3761-J TRF3761-K layout_lws181.gif
A. Refer to the Loop Filter Design section.
Figure 91. TRF3761 Layout