SLLSG07 March   2025 TUSB1044A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 USB 3.2 x2 Description
      3. 7.3.3 DisplayPort
      4. 7.3.4 4-Level Inputs
      5. 7.3.5 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 Modes
    5. 7.5 Programming
      1. 7.5.1 Procedure to Write to TUSB1044A I2C Registers:
      2. 7.5.2 Procedure to Read the TUSB1044A I2C Registers:
      3. 7.5.3 Procedure to Set a Starting Sub-Address for I2C Reads:
  9. 8 Register Maps
    1. 8.1 TUSB1044A Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 ESD Protection
      4. 9.2.4 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.2 only (USB/DP Alternate Mode)
      2. 9.3.2 USB3.2 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
      4. 9.3.4 USB 3.2 Only (USB/Custom Alternate Mode)
      5. 9.3.5 USB3.2 and 1 Lane of Custom Alt Mode
      6. 9.3.6 USB3.2 and 2 Lanes of Custom Alt Mode
      7. 9.3.7 USB3.2 and 4 Lanes of Custom Alt Mode
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TUSB1044A RNQ Package40-Pin (WQFN)Top ViewFigure 4-1 RNQ Package40-Pin (WQFN)Top View
Pin Functions
PINTYPEDESCRIPTION
NO.NAME
1VCCP3.3V power supply
2UEQ1/A14 Level IThis pin along with UEQ0 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1, UTX2 receivers. In I2C Mode, this pin also sets the TUSB1044A I2C address. See also Table 7-10.
3CFG04 Level ICFG0. This pin along with CFG1 selects the VOD linearity range and DC gain for all the downstream and upstream channels. Refer to Table 7-9 for VOD linearity range and DC gain options.
4CFG14 Level ICFG1. This pin along with CFG0 sets the VOD linearity range and DC gain for all the downstream and upstream channels. Refer to Table 7-9 for VOD linearity range and DC gain options.
5SWAP2 Level I
(PD)		This pin swaps all the channel directions and EQ settings of downstream facing and upstream facing data path inputs.
0 – Do not swap channel directions and EQ settings (Default)
1. – Swap channel directions and EQ settings.
6VCCP3.3V power supply
7SLP_S0#2 Level I
(PD)		This pin when asserted low disables the Receiver Detect functionality. While this pin is low and TUSB1044A is in U2/U3, the TUSB1044A disables the LOS and LFPS detection circuitry and the RX termination for both channels remains enabled. If this pin is low and the TUSB1044A is in the disconnect state, the RX detect functionality is disabled and RX termination for both channels is disabled.
0 – RX Detect disabled
1 – RX Detect enabled (Default)
8DIR02 Level I
(PD)		This pin along with DIR1 sets the data path signal direction format. Refer to Table 7-5 for signal direction formats.
0 - Source Side (DFP) Alt Mode format
1 - Sink Side (UFP) Alt Mode format
9URX2pDiff I/ODifferential positive input/output for upstream facing RX2 port.
10URX2nDiff I/ODifferential negative input/output for upstream facing RX2 port.
11DIR12 Level I/O
(PD)		This pin along with DIR0 sets the data path signal direction format. Refer to Table 7-5 for signal direction formats.
0 - DisplayPort Alt Mode format
1 - Custom Alt Mode format
12UTX2pDiff I/ODifferential positive input/output for upstream facing TX2 port.
13UTX2nDiff I/ODifferential negative input/output for upstream facing TX2 port.
14VIO_SEL4 Level I/OThis pin selects I/O voltage levels for the 2-level GPIO configuration pins and the I2C interface:
0 = 3.3V configuration I/O voltage, 3.3V I2C interface (Default)
R = 3.3V configuration I/O voltage, 1.8V I2C interface
F = 1.8V configuration I/O voltage, 3.3V I2C interface
1 = 1.8V configuration I/O voltage, 1.8V I2C interface.
15UTX1nDiff I/ODifferential negative input/output for upstream facing TX1 port.
16UTX1pDiff I/ODifferential positive input/output for upstream facing TX1 port.
17I2C_EN4 Level II2C Programming or Pin Strap Programming Select.
0 = GPIO Mode, AUX Snoop Enabled (I2C disabled)
R = TI Test Mode (I2C enabled)
F = GPIO Mode, AUX Snoop Disabled (I2C disabled)
1 = I2C enabled.
18URX1nDiff I/ODifferential negative input/output for upstream facing RX1 port.
19URX1pDiff I/ODifferential positive input/output for upstream facing RX1 port.
20VCCP3.3V power supply
21FLIP/SCL2 Level I
(PD)
(Failsafe)		In GPIO mode, this is Flip control pin. Otherwise, this pin is I2C clock.
22CTL0/SDA2 Level I
(PD)
(Failsafe)		In GPIO mode, this is a USB3.2 Switch control pin. Otherwise, this pin is I2C data.
23CTL12 Level I
(PD)		DP Alt mode Switch Control Pin. In GPIO mode, this pin enables or disables the DisplayPort functionality. Otherwise, DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
In I2C Mode, this pin is not used by TUSB1044A.
24AUXpI/O,
CMOS		AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC-coupling capacitor. In addition to an AC-coupling capacitor, this pin also requires a 100kΩ resistor to GND between the AC-coupling capacitor and the AUXp pin if the TUSB1044A is used on the DisplayPort source side, or a 1MΩ resistor to DP_PWR (3.3V) between the AC-coupling capacitor and the AUXp pin if the TUSB1044A is used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB1044A for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug.
25AUXnI/O,
CMOS		AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC-coupling capacitor. In addition to the AC-coupling capacitor, this pin also requires a 100kΩ resistor to DP_PWR (3.3V) between the AC-coupling capacitor and the AUXn pin if the TUSB1044A is used on the DisplayPort source side, or a 1MΩ resistor to GND between the AC-coupling capacitor and the AUXn pin if the TUSB1044A is used on the DisplayPort sink side. This pin along with AUXp is used by the TUSB1044A for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug.
26SBU2I/O,
CMOS		SBU2. When the TUSB1044A is used on the DisplayPort source side, DC couple this pin to the SBU2 pin of the Type-C receptacle. When the TUSB1044A is used on the DisplayPort sink side, DC couple this pin to the SBU1 pin of the Type-C receptacle. A 2MΩ resistor to GND is also recommended.
27SBU1I/O,
CMOS		SBU1. When the TTUSB1044A is used on the DisplayPort source side, DC couple this pin to the SBU1 pin of the Type-C receptacle. When the TUSB1044A is used on the DisplayPort sink side, DC couple this pin to the SBU2 pin of the Type-C receptacle. A 2MΩ resistor to GND is also recommended.
28VCCP3.3V power supply
29DEQ14 Level IThis pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2, DTX1, DTX2 receivers.
30DRX1pDiff I/ODifferential positive input/output for downstream facing RX1 port.
31DRX1nDiff I/ODifferential negative input/output for downstream facing RX1 port.
32HPDIN2 Level I
(PD)		This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater than 2ms, all DisplayPort lanes are disabled and AUX to SBU switch remains closed. When HPDIN is high, the enabled DisplayPort lanes from AUX snoop or registers are active.
33DTX1pDiff I/ODifferential positive input/output for downstream facing TX1 port.
34DTX1nDiff I/ODifferential negative input/output for downstream facing TX1 port.
35UEQ0/A04 Level IThis pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1, UTX2 receivers. In I2C mode, this pin also sets the TUSB1044A I2C address. See also Table 7-10.
36DTX2nDiff I/ODifferential negative input/output for downstream facing TX2 port.
37DTX2pDiff I/ODifferential positive input/output for downstream facing TX2 port.
38DEQ04 Level IThis pin along with DEQ1 sets the high-frequency equalizer gain for downstream facing URX1, URX2, UTX1, UTX2 receivers.
39DRX2nDiff I/ODifferential negative input/output for downstream facing RX2 port.
40DRX2pDiff I/ODifferential positive input/output for downstream facing RX2 port.
Thermal PadGNDGround