SLLSG07 March   2025 TUSB1044A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 USB 3.2 x2 Description
      3. 7.3.3 DisplayPort
      4. 7.3.4 4-Level Inputs
      5. 7.3.5 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 Modes
    5. 7.5 Programming
      1. 7.5.1 Procedure to Write to TUSB1044A I2C Registers:
      2. 7.5.2 Procedure to Read the TUSB1044A I2C Registers:
      3. 7.5.3 Procedure to Set a Starting Sub-Address for I2C Reads:
  9. 8 Register Maps
    1. 8.1 TUSB1044A Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 ESD Protection
      4. 9.2.4 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.2 only (USB/DP Alternate Mode)
      2. 9.3.2 USB3.2 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
      4. 9.3.4 USB 3.2 Only (USB/Custom Alternate Mode)
      5. 9.3.5 USB3.2 and 1 Lane of Custom Alt Mode
      6. 9.3.6 USB3.2 and 2 Lanes of Custom Alt Mode
      7. 9.3.7 USB3.2 and 4 Lanes of Custom Alt Mode
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Receiver Linear Equalization

The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in the system. The receiver overcomes these losses by attenuating the low-frequency components of the signals with respect to the high-frequency components. Select the proper gain setting to match the channel insertion loss. Two 4-level input pins enable up to 16 possible equalization settings. The upstream path and the downstream path each have two 4-level inputs for equalization settings; UEQ[1:0] and DEQ[1:0] respectively. The TUSB1044A also provides the flexibility of adjusting equalization settings through I2C registers URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL for each individual channel and for each direction (upstream or downstream).