SLLSG07 March   2025 TUSB1044A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 USB 3.2 x2 Description
      3. 7.3.3 DisplayPort
      4. 7.3.4 4-Level Inputs
      5. 7.3.5 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration in I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Custom Alternate Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 Adjustable VOD Linear Range and DC Gain
      7. 7.4.7 USB3.1 Modes
    5. 7.5 Programming
      1. 7.5.1 Procedure to Write to TUSB1044A I2C Registers:
      2. 7.5.2 Procedure to Read the TUSB1044A I2C Registers:
      3. 7.5.3 Procedure to Set a Starting Sub-Address for I2C Reads:
  9. 8 Register Maps
    1. 8.1 TUSB1044A Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 ESD Protection
      4. 9.2.4 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.2 only (USB/DP Alternate Mode)
      2. 9.3.2 USB3.2 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
      4. 9.3.4 USB 3.2 Only (USB/Custom Alternate Mode)
      5. 9.3.5 USB3.2 and 1 Lane of Custom Alt Mode
      6. 9.3.6 USB3.2 and 2 Lanes of Custom Alt Mode
      7. 9.3.7 USB3.2 and 4 Lanes of Custom Alt Mode
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.5.1 Layout Guidelines

  1. Route RXP/N and TXP/N pairs with controlled 90Ω differential impedance (± 15%).
  2. Keep away from other high speed signals.
  3. Keep intra-pair routing to within 2 mils.
  4. Make sure length matching is near the location of mismatch.
  5. Separate each pair at least by 3 times the signal trace width.
  6. Keep the use of bends in differential traces to a minimum. When bends are used, make sure the number of left and right bends are as equal as possible and that the angle of the bend is ≥ 135 degrees. This setup can minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
  7. Route all differential pairs on the same of layer.
  8. Keep the number of VIAS to a minimum. TI recommends to have no more than 1 VIA between TUSB1044A and Type-C connector and no more than 1 VIA between TUSB1044A and USB3.1 Device/Host.
  9. Keep traces on layers adjacent to ground plane.
  10. Do NOT route differential pairs over any plane split.
  11. Remember that adding test points can cause impedance discontinuity; and therefore, negatively impacts signal performance. If test points are used, place the test points in series and symmetrically. The test points must not be placed in a manner that causes a stub on the differential pair.
  12. Assuming 1dB/inch loss at 5GHz, make sure the trace length between TUSB1044A and Type-C connector is no more than 1.5 inches.
  13. Assuming 1dB/inch loss at 5GHz, make sure the trace length between TUSB1044A and the USB 3.1 Host/Device is no more than 8 inches.
  14. Select ESD protection devices and EMI suppression devices carefully, and make sure these devices have excellent transient performance at 10Gbps with flat shunt capacitance characteristics over ±650mV voltage range. Note small-signal insertion loss characteristics are insufficient to determine suitability of non-linear devices (ESD devices) for 10Gbps operation