SLLSEF7 March   2014 TUSB8020B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
        1. 8.3.4.1 Crystal Requirements
        2. 8.3.4.2 Input Clock Requirements
      5. 8.3.5 Power Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1 Configuration Registers
        1. 8.5.1.1  ROM Signature Register
        2. 8.5.1.2  Vendor ID LSB Register
        3. 8.5.1.3  Vendor ID MSB Register
        4. 8.5.1.4  Product ID LSB Register
        5. 8.5.1.5  Product ID MSB Register
        6. 8.5.1.6  Device Configuration Register
        7. 8.5.1.7  Battery Charging Support Register
        8. 8.5.1.8  Device Removable Configuration Register
        9. 8.5.1.9  Port Used Configuration Register
        10. 8.5.1.10 PHY Custom Configuration Register
        11. 8.5.1.11 Device Configuration Register 2
        12. 8.5.1.12 UUID Registers
        13. 8.5.1.13 Language ID LSB Register
        14. 8.5.1.14 Language ID MSB Register
        15. 8.5.1.15 Serial Number String Length Register
        16. 8.5.1.16 Manufacturer String Length Register
        17. 8.5.1.17 Product String Length Register
        18. 8.5.1.18 Serial Number Registers
        19. 8.5.1.19 Manufacturer String Registers
        20. 8.5.1.20 Product String Registers
        21. 8.5.1.21 Additional Feature Configuration Register
        22. 8.5.1.22 Charging Port Control Register
        23. 8.5.1.23 Device Status and Command Register
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 VBUS Power Switch Implementation
        5. 9.2.2.5 Clock, Reset, and Misc
        6. 9.2.2.6 Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
      3. 11.2.3 Thermal Pad
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Applications and Implementation

9.1 Application Information

The TUSB8020B-Q1 is a two-port USB 3.0 compliant hub. It provides simultaneous SuperSpeed USB and high-speed/full-speed connections on the upstream port and provides SuperSpeed USB, high-speed, full-speed, or low speed connections on the downstream port. The TUSB8020B-Q1 can be used in any application that needs additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By using the TUSB8020B-Q1, the notebook can increase the downstream port count to three.

9.2 Typical Applications

A common application for the TUSB8020B-Q1 is as a self powered standalone USB hub product. The product is powered by an external 5V DC Power adapter. In this application, using a USB cable TUSB8020B-Q1’s upstream port is plugged into a USB Host controller. The downstream ports of the TUSB8020B-Q1 are exposed to users for connecting USB hard drives, camera, flash drive, and so forth.

discrete_usb_hub_llsef7.gifFigure 3. Discrete USB Hub Product

9.2.1 Design Requirements

Table 50. Input Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDD Supply 1.1V
VDD33 Supply 3.3V
Upstream Port USB Support (SS, HS, FS) SS, HS, FS
Downstream Port 1 USB Support (SS, HS, FS, LS) SS, HS, FS, LS
Downstream Port 2 USB Support (SS, HS, FS, LS) SS, HS, FS, LS
# of Removable Downstream Ports 2
# of Non-Removable Downstream Ports 0
Full Power Management of Downstream Ports Yes. (FULLPWRMGMTZ = 0)
Individual Control of Downstream Port Power Switch Yes. (GANGED = 0)
Power Switch Enable Polarity Active High. (PWRCTL_POL = 0)
Battery Charge Support for Downstream Port 1 Yes
Battery Charge Support for Downstream Port 2 Yes
I2C EEPROM Support No.
24MHz Clock Source Crystal

9.2.2 Detailed Design Procedure

9.2.2.1 Upstream Port Implementation

The upstream of the TUSB8020B-Q1 is connected to a USB3 Type B connector. This particular example has GANGED terminal and FULLPWRMGMTZ terminal pulled low which results in individual power support each downstream port. The VBUS signal from the USB3 Type B connector is feed through a voltage divider. The purpose of the voltage divider is to make sure the level meets USB_VBUS input requirements.

upstream_porta_sllsef7.gifFigure 4. Upstream Port Implementation

9.2.2.2 Downstream Port 1 Implementation

The downstream port 1 of the TUSB8020B-Q1 is connected to a USB3 Type A connector. With BATEN1 terminal pulled up, Battery Charge support is enabled for Port 1. If Battery Charge support is not needed, then pull-up resistor on BATEN1 should be uninstalled. The PWRCTL_POL is pulled down which will result in active high power enable (PWRCTL1 and PWRCTL2) for a USB VBUS power switch.

downstream_port1a_sllsef7.gifFigure 5. Downstream Port 1 Implementation

9.2.2.3 Downstream Port 2 Implementation

The downstream port 2 of the TUSB8020B-Q1 is connected to a USB3 Type A connector. With BATEN2 terminal pulled up, Battery Charge support is enabled for Port 2. If Battery Charge support is not needed, then pull-up resistor on BATEN2 should be uninstalled.

downstream_port2a_sllsef7.gifFigure 6. Downstream Port 2 Implementation

9.2.2.4 VBUS Power Switch Implementation

This particular example uses the Texas Instruments TPS2561 dual channel precision adjustable current-limited power switch. For details on this power switch or other power switches available from Texas Instruments, please refer to the Texas Instruments website.

vbus_pwr_switcha_sllsef7.gifFigure 7. Power Switch Implementation

9.2.2.5 Clock, Reset, and Misc

clock_reset_misca_sllsef7.gifFigure 8. Clock, Reset, and Misc

9.2.2.6 Power Implementation

pwr_impa_sllsef7.gifFigure 9. Power Implementation

9.2.3 Application Curves

ss_ds1_sllsef7.gifFigure 10. SuperSpeed TX Eye for Downstream Port 1
hs_ds1_b_sllsef7.gifFigure 12. : HighSpeed TX Eye for Downstream Port 1
ss_ds2_sllsef7.gifFigure 11. : SuperSpeed TX Eye for Downstream Port 2
hs_ds2_b_sllsef7.gifFigure 13. HighSpeed TX Eye for Downstream Port 2