SLLSEF7 March   2014 TUSB8020B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
        1. 8.3.4.1 Crystal Requirements
        2. 8.3.4.2 Input Clock Requirements
      5. 8.3.5 Power Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1 Configuration Registers
        1. 8.5.1.1  ROM Signature Register
        2. 8.5.1.2  Vendor ID LSB Register
        3. 8.5.1.3  Vendor ID MSB Register
        4. 8.5.1.4  Product ID LSB Register
        5. 8.5.1.5  Product ID MSB Register
        6. 8.5.1.6  Device Configuration Register
        7. 8.5.1.7  Battery Charging Support Register
        8. 8.5.1.8  Device Removable Configuration Register
        9. 8.5.1.9  Port Used Configuration Register
        10. 8.5.1.10 PHY Custom Configuration Register
        11. 8.5.1.11 Device Configuration Register 2
        12. 8.5.1.12 UUID Registers
        13. 8.5.1.13 Language ID LSB Register
        14. 8.5.1.14 Language ID MSB Register
        15. 8.5.1.15 Serial Number String Length Register
        16. 8.5.1.16 Manufacturer String Length Register
        17. 8.5.1.17 Product String Length Register
        18. 8.5.1.18 Serial Number Registers
        19. 8.5.1.19 Manufacturer String Registers
        20. 8.5.1.20 Product String Registers
        21. 8.5.1.21 Additional Feature Configuration Register
        22. 8.5.1.22 Charging Port Control Register
        23. 8.5.1.23 Device Status and Command Register
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 VBUS Power Switch Implementation
        5. 9.2.2.5 Clock, Reset, and Misc
        6. 9.2.2.6 Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
      3. 11.2.3 Thermal Pad
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 Power Supply

VDD should be implemented as a single power plane, as should VDD33.

  • The VDD terminals of the TUSB8020B-Q1 supply 1.1 V (nominal) power to the core of the TUSB8020B-Q1. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device due to the high current draw on the power rail. The output of the core voltage regulator may need to be adjusted to account for this or a ferrite bead with low DC resistance (less than 0.05 Ω) can be selected.
  • The VDD33 terminals of the TUSB8020B-Q1 supply 3.3-V power rail to the I/O of the TUSB8020B-Q1. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • All power rails require a 10-µF capacitor or 1-µF capacitors for stability and noise immunity. These bulk capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as close to the TUSB8020B-Q1 power pins as possible with an optimal grouping of two of differing values per pin.

10.2 Downstream Port Power

  • The downstream port power, VBUS, must be supplied by a source capable of supplying 5 V and at least
    900 mA per port. Downstream port power switches can be controlled by the TUSB8020BPHP signals. It is also possible to leave the downstream port power always enabled.
  • A large bulk low-ESR capacitor of 22 µF or larger is required on each downstream port’s VBUS to limit in-rush current.
  • The ferrite beads on the VBUS pins of the downstream USB port connections are recommended for both ESD and EMI reasons. A 0.1-µF capacitor on the USB connector side of the ferrite provides a low impedance path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.

10.3 Ground

It is recommended that only one board ground plane be used in the design. This provides the best image plane for signal traces running above the plane. The thermal pad of the TUSB8020B-Q1 and any of the voltage regulators should be connected to this plane with vias. An earth or chassis ground is implemented only near the USB port connectors on a different plane for EMI and ESD purposes.