SLUSBL6 February   2015 UCC24650

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO Block
      2. 7.3.2 PCD
      3. 7.3.3 Sample, Hold, and Transient Detector
      4. 7.3.4 Wake Pulse Generator and WAKE Switch
      5. 7.3.5 PCD Counter and ENS Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

There are no critical layout requirements. TI recommends to use the usual industry good-practice layout guidelines and principles.

To increase the reliability and feasibility of the project, TI recommends adhering to the following guidelines for PCB layout:

  • Connect the WAKE and GND signals close to the output rectifier pads to minimize the effect of high di/dt and stray inductance on the WAKE pin voltage at the beginning of the flyback demagnetization time. It is not so important to minimize the WAKE and GND sense track lengths, rather to minimize the inductance between the two sense points at the rectifier.
  • If ENS is not used, connect it to the GND pin to prevent the ENS input voltage from going below GND due to possible system noise.

10.2 Layout Example

The partial layout example of Figure 25 demonstrates an effective component and track arrangement for low-noise operation on a single-layer PCB. Actual board layout must conform to the constraints on a specific design, so many variations are possible.

ai_layout_lusbl6.gifFigure 25. UCC24650 Partial Layout Example