SLUSBL6 February   2015 UCC24650

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO Block
      2. 7.3.2 PCD
      3. 7.3.3 Sample, Hold, and Transient Detector
      4. 7.3.4 Wake Pulse Generator and WAKE Switch
      5. 7.3.5 PCD Counter and ENS Switch
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23
Top View
pin_lusbl6.gif
A. (N.C. = No connection internally)

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
VDD 1 P VDD is the bias supply input pin to the controller. This pin is continuously monitored to detect when the VDD voltage droops by approximately –3% of the previously sampled level. The VDD level is sampled and stored at the end of each power cycle generated by the PSR. The device is disabled when the VDD voltage is below the UVLO threshold.
GND 2 G The ground pin is both the reference pin for the controller and the low-side return for the WAKE output. Take special care to return all AC decoupling capacitors as close as possible to this pin and avoid any common trace length with analog signal return paths.
ENS 3 O Enable secondary circuit is an open-drain MOSFET output that enables a compatible synchronous rectifier (SR) controller or other secondary-side circuitry. ENS is open during normal operation and becomes low-impedance to GND when each switching period remains greater than tDISS (177 µs typical) for 63 consecutive cycles. ENS becomes high-impedance again when the switching period operates at less than tENS (57 µs typical) for 32 cumulative cycles. If the ENS function is not used, this terminal should be connected to GND.
N/C 4 — The no-connection pin has no internal electrical connection.
WAKE 5 I/O WAKE is a multi-function pin which connects to the transformer secondary winding, directly across the ground-referenced diode or rectifier. As an input, it monitors voltage pulses due to primary-side controller activity and triggers sampling of the VDD voltage at the end of each power cycle. When the WAKE voltage falls below 55 mV for >500 ns, the device becomes armed to deliver a power cycle detect (PCD) pulse internally. When the WAKE voltage subsequently rises above 55 mV, a PCD pulse is delivered to reset the oscillator, clock the PCD counter, and trigger a new sample of the VDD voltage. If the VDD voltage droops to 97% of the last sampled value, WAKE is driven as an output. As an output, it injects current into the transformer winding for 1 µs at a 33-kHz rate until a power cycle is detected. The maximum magnitude that this current may achieve is limited internally.
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output