SLUSDX3C november   2020  – august 2023 UCC25800-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Oscillator
      3. 8.3.3 External Synchronization
      4. 8.3.4 Dead-Time
        1. 8.3.4.1 Adaptive Dead-time
        2. 8.3.4.2 Maximum Programmable Dead-time
      5. 8.3.5 Protections
        1. 8.3.5.1 Overcurrent Protection
          1. 8.3.5.1.1 OCP Threshold Setting
          2. 8.3.5.1.2 Output Power Capability
        2. 8.3.5.2 Input Overvoltage Protection (OVP)
        3. 8.3.5.3 Over-Temperature Protection (TSD)
        4. 8.3.5.4 Pin-Fault Protections
        5. 8.3.5.5 VREG Pin Protection
      6. 8.3.6 DIS/FLT Pin operation
        1. 8.3.6.1 FAULT Codes
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Soft-start Mode
      3. 8.4.3 Normal Operation Mode
      4. 8.4.4 Disabled Mode
      5. 8.4.5 Fault Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 LLC Converter Operation Principle
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Power Management

The VCC pin powers the UCC25800-Q1 transformer driver. When the VCC pin voltage is below the UVLO rising threshold (UVLOR), the VREG pin 5-V regulator is disabled (VREG = 0 V). After the VCC pin voltage exceeds UVLOR, the 5-V regulator is enabled and VREG pin rises, while the DIS/FLT pin is internally pulled low through an internal 750-μA current source, (DIS/FLT = 0 V). When the VREG exceeds 4.5 V (VREGOK), the DIS/FLT pin is released. If the DIS/FLT pin is not pulled low externally, it rises to VREG pin voltage level via an internal 100-kΩ pull up resistor. When DIS/FLT pin voltage exceeds the rising enable threshold (ENTH), the internal regulators and references are turned on and the transformer driver reads the Thevenin resistance on the OC/DT pin to set the overcurrent protection (OCP) thresholds. After this process completes, the faults are checked and if they are all cleared, the oscillator is enabled and the power stage starts switching. The time to complete this process is approximately 500 μs.

If a fault is detected, the transformer driver activates the internal pull-down current source on the DIS/FLT pin, the power stage stops switching, and the device outputs the fault code.

The rise time of the DIS/FLT pin depends on the external loading on the pin. An external pull-up can be added to the pin if there is concern over noise immunity. The values are specified in Section 8.3.6.

When the VCC pin voltage is above the UVLOR threshold and DIS/FLT pin is pulled low externally the transformer driver remains disabled with IVCCDIS = 660 µA.

If after a completed power-up sequence, VCC falls below the UVLO falling threshold (UVLOF), the power stage switching is immediately stopped. The VREG pin voltage regulator is disabled making the VREG pin voltage fall.

The VCC pin current is a combination of the IC bias current and the power stage current. It is important to have a low ESL bypass capacitor to minimize the current loop among this capacitor and VCC, GND pins. Refer to Section 11 for details.