SLUS545E November   2002  – December 2015 UCC27423 , UCC27424 , UCC27425

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 9.2.2.2 Parallel Outputs
        3. 9.2.2.3 VDD
        4. 9.2.2.4 Drive Current and Power Requirements
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Products
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The UCC2742x family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. Three standard logic options are offered – dual-inverting, dual-noninverting and one-inverting and one-noninverting driver. The thermally enhanced 8-pin PowerPAD™ MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard SOIC-8 (D) or PDIP-8 (P) packages. Using a design that inherently minimizes shoot-through current, these drivers deliver 4A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique Bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. Table 1 highlights more details about UCC2742x.

Table 1. UCC2742x Features and Benefits

FEATURE BENEFIT
1-ns (typ) delay matching between channels Ease of paralleling outputs for higher (2 times) current capability, ease of driving parallel-power switches
Expanded VDD operating range of 4 to 15 V Flexibility in system design
Outputs enabled when enable pins (ENx) in floating condition Pin-to-pin compatibility with the UCC27324 device from Texas Instruments and industry standard pinout, in designs where Pin 1 and Pin 8 are in floating condition
CMOS/TTL compatible input and enable threshold with wide hysteresis Enhanced noise immunity, while retaining compatibility with microcontroller logic-level inputs signals (3.3 V, 5 V) optimized for digital power
Ability to handle –5 VDC (max) at input pins (INA/B) Increased robustness in noisy environments

8.2 Functional Block Diagram

UCC27423 UCC27424 UCC27425 UDG-01063_lus545.gif

8.3 Feature Description

8.3.1 Enable

UCC2742x provides dual Enable inputs for improved control of each driver channel operation. The inputs incorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100kΩ resistor for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when ENBA and ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver and therefore can be left open for standard operation. However, if the enable pin is left open, it is recommended to terminate any PCB traces to be as short as possible to limit noise.  If large noise is present due to non-optimal PCB layout, it is recommended to tie the Enable pin to Vcc or to add a filter capacitor (0.1 µF) to the Enable pin. The output states when the drivers are disabled is low regardless of the input state. See the truth table of Table 2 for the operation using enable logic.

Enable input are compatible with both logic signals and slow changing analog signals. They can be directly driven or a power-up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and ENBB control input A and input B respectively.

8.3.2 Input Stage

The input thresholds have 3.3 V logic sensitivity over the full range of VDD voltages; it is equally compatible with 0 to VDD signals. The inputs of the UCC2742x driver family are designed to withstand 500-mA reverse current without damaging the IC for logic upset. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function as a digital gate, and they are not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.

Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limited rise or fall times to the power device is desired, an external resistance can be added between the output of the driver and the load device which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the device package, as discussed in the section on Thermal Considerations.

Importantly, input signal of the two channels, INA and INB, which has logic compatible threshold and hysteresis. If not used, INA and INB must be tied to either VDD or GND; it must not be left floating.

8.3.3 Output Stage

Inverting output s of the UCC27423 and OUTA of the UCC27425 are intended to drive external P-channel MOSFETs. Noninverting outputs of the UCC27424 and OUTB of the UCC27425 are intended to drive external N-Channel MOSFETs. Each output stage is capable of supplying ±4 A peak current pulses and swings to both VDD and GND. The pullup/pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external-Schottky-clamp diodes are not required. The UCC2742x family delivers 4 A of gate drive where it is most needed during the MOSFET switching transition (at the Miller plateau region) providing improved efficiency gains. A unique Bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.

8.4 Device Functional Modes

With VDD power supply in the range of 4 V to 16 V, the output stage is dependent on the states of the HI and LI pins. Table 2 shows the UCC2742x truth table.

Table 2. Input/Output Logic

INPUTS (VIN_L, VIN_H) UCC27423 UCC27424 UCC27425
ENBA ENBB INA INB OUTA OUTB OUTA OUTB OUTA OUTB
H H L L H H L L H L
H H L H H L L H H H
H H H L L H H L L L
H H H H L L H H L H
L L X X L L L L L L

Importantly, if INA and INB are not used, they must be tied to either VDD or GND; it must not be left floating.