The UCC2742x family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. Three standard logic options are offered – dual-inverting, dual-noninverting, and one-inverting and one-noninverting driver. The thermally enhanced 8-pin PowerPAD™ MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard SOIC-8 (D) or PDIP-8 (P) packages.
Using a design that inherently minimizes shoot-through current, these drivers deliver 4A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique BiPolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.
The UCC2742x provides enable (ENB) functions to have better control of the operation of the driver applications. ENBA and ENBB are implemented on pins 1 and 8 which were previously left unused in the industry standard pin-out. They are internally pulled up to VDD for active high logic and can be left open for standard operation.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | UCC2742x Dual 4-A High Speed Low-Side MOSFET Drivers With Enable datasheet (Rev. E) | PDF | HTML | 31 Dec 2015 |
| Technical article | Managing power-supply noise with a 30-V gate driver | 07 Dec 2021 | ||
| Application note | Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver | PDF | HTML | 10 Nov 2021 | |
| Application note | External Gate Resistor Selection Guide (Rev. A) | 28 Feb 2020 | ||
| Application note | Understanding Peak IOH and IOL Currents (Rev. A) | 28 Feb 2020 | ||
| More literature | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | 29 Oct 2018 | ||
| Technical article | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | 19 Sep 2018 | ||
| Selection guide | Power Management Guide 2018 (Rev. R) | 25 Jun 2018 | ||
| Technical article | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | 30 May 2018 | ||
| Technical article | Boosting efficiency for your solar inverter designs | 24 May 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | Download |
|---|---|---|
| HVSSOP (DGN) | 8 | View options |
| PDIP (P) | 8 | View options |
| SOIC (D) | 8 | View options |
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