SLUS545E November   2002  – December 2015 UCC27423 , UCC27424 , UCC27425

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 9.2.2.2 Parallel Outputs
        3. 9.2.2.3 VDD
        4. 9.2.2.4 Drive Current and Power Requirements
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Products
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

D Package, DGN Package, P Package
8-Pin SOIC, 8-PIn MSOP-PowerPAD, 8-Pin PDIP
Top View
UCC27423 UCC27424 UCC27425 po_lus545.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ENBA 1 I Enable input for the driver A with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100 kΩ resistor for active high operation. The output state when the device is disabled will be low regardless of the input state.
ENBB 8 I Enable input for the driver B with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100 kΩ resistor for active high operation. The output state when the device is disabled will be low regardless of the input state.(1)
GND 3 Common ground: this ground should be connected very closely to the source of the power MOSFET which the driver is driving.
INA 2 I Input A: input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating.(1)
INB 4 I Input B. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating.
OUTA 7 O Driver output A. The output stage is capable of providing 4A drive current to the gate of a power MOSFET.
OUTB 5 O Driver output B. The output stage is capable of providing 4A drive current to the gate of a power MOSFET.
VDD 6 I Supply. Supply voltage and the power input connection for this device.
(1) Refer to Detailed Description for more details.