SLUS545E November   2002  – December 2015 UCC27423 , UCC27424 , UCC27425

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 9.2.2.2 Parallel Outputs
        3. 9.2.2.3 VDD
        4. 9.2.2.4 Drive Current and Power Requirements
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Products
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

The recommended bias supply voltage range for UCC2742x is from 4 V to 15 V. The upper end of this range is driven by the 16 V absolute maximum voltage rating of the VDD. It is recommended to keep proper margin to allow for transient voltage spikes.

A local bypass capacitor should be placed between the VDD and GND pins. And this capacitor should be located as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. TI recommends using 2 capacitors across VDD and GND: a 100 nF ceramic surface-mount capacitor for high frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10 μF, for IC bias requirements.