SLUS545E November   2002  – December 2015 UCC27423 , UCC27424 , UCC27425

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 9.2.2.2 Parallel Outputs
        3. 9.2.2.3 VDD
        4. 9.2.2.4 Drive Current and Power Requirements
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Products
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VDD Supply voltage –0.3 16 V
IOUT_DC Output current (OUTA, OUTB) DC 0.2 A
IOUT_PULSED Pulsed, (0.5 μs) 4.5 A
VIN Input voltage (INA, INB) –5 6 or VDD + 0.3 (whichever is larger) V
Enable voltage (ENBA, ENBB) –0.3 6 or VDD + 0.3 (whichever is larger) V
Power dissipation at TA = 25°C DGN package 3 W
D package 650 mW
P package 350
TJ Junction operating temperature –55 150 °C
Lead temperature (soldering, 10 s) 300 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When VDD ≤ 6 V, EN rating max value is 6 V; when VDD > 6 V, EN rating max value is VDD + 0.3 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 4 15 V
INA and INB Input voltage –2 15 V
ENA and ENB Enable voltage 0 15 V
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) UCC2742x UNIT
D (SOIC) DGN (MSOP) P (PDIP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 107.3 56.6 55.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.2 52.8 45.3 °C/W
RθJB Junction-to-board thermal resistance 47.3 32.6 32.6 °C/W
ψJT Junction-to-top characterization parameter 10.2 1.8 23.0 °C/W
ψJB Junction-to-board characterization parameter 46.8 32.3 32.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance – 5.9 – °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VDD = 4.5 V to 15 V, TA = –40°C to 125°C,TA = TJ, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT (INA, INB)
VIN_H Logic 1 input threshold 2 V
VIN_L Logic 0 input threshold 1
Input current 0 V ≤ VIN ≤ VDD –10 0 10 μA
OUTPUT (OUTA, OUTB)
Output current VDD = 14 V (1) 4 A
VOH High-level output voltage VOH = VDD – VOUT, IOUT = –10 mA 330 450 mV
VOL Low-level output level IOUT = 10 mA 22 45
Output resistance high TA = 25°C, IOUT = –10 mA, VDD = 14 V(2) 25 30 35 Ω
TA = full range, IOUT = –10 mA, VDD = 14 V(2) 18 45
Output resistance low TA = 25°C, IOUT = 10 mA, VDD = 14 V(2) 1.9 2.2 2.5
TA = full range IOUT = 10 mA, VDD = 14 V(2) 1.2 4.0
Latch-up protection 500 mA
SWITCHING TIME
tr Rise time (OUTA, OUTB) CLOAD = 1.8 nF 20 40 ns
tf Fall time (OUTA, OUTB) CLOAD = 1.8 nF 15 40
td1 Delay, IN rising (IN to OUT) CLOAD = 1.8 nF 25 40
td2 Delay, IN falling (IN to OUT) CLOAD = 1.8 nF 35 50
ENABLE (ENBA, ENBB)
VIN_H High-level input voltage LO to HI transition 1.7 2.4 2.9 V
VIN_L Low-level input voltage HI to LO transition 1.1 1.8 2.2 V
Hysteresis 0.15 0.55 0.90 V
RENB Enable impedance VDD = 14 V, ENB = GND 75 100 140 kΩ
tD3 Propagation delay time (see Figure 2) CLOAD = 1.8 nF 30 60 ns
tD4 Propagation delay time (see Figure 2) CLOAD = 1.8 nF 100 150 ns
OVERALL
IDD UCC27423
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V		 INA = 0 V, INB = 0 V 900 1350 μA
INA = 0 V, INB = HIGH 750 1100
INA = HIGH, INB = 0 V 750 1100
INA = HIGH, INB = HIGH 600 900
IDD UCC27424
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V		 INA = 0 V, INB = 0 V 300 450 μA
INA = 0 V, INB = HIGH 750 1100
INA = HIGH, INB = 0 V 750 1100
INA = HIGH, INB = HIGH 1200 1800
IDD UCC27425
Static operating current, VDD = 15 V,
ENBA = ENBB = 15 V		 INA = 0 V, INB = 0 V 600 900 μA
INA = 0 V, INB = HIGH 1050 1600
INA = HIGH, INB = 0 V 450 700
INA = HIGH, INB = HIGH 900 1350
IDD All disabled, VDD = 15 V,
ENBA = ENBB = 0 V		 INA = 0 V, INB = 0 V 300 450 μA
INA = 0 V, INB = HIGH 450 700
INA = HIGH, INB = 0 V 450 700
INA = HIGH, INB = HIGH 600 900
(1) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors.
(2) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

7.6 Dissipation Ratings

PACKAGE SUFFIX POWER RATING (mW)
TA = 70°C(1) 		DERATING FACTOR ABOVE
70°C (mW/°C)(1)
SOIC-8 D 344–655(2) 6.25–11.9(2)
PDIP-8 P 500 9
MSOP(3) DGN 1370 17.1
(1) 125°C operating junction temperature is used for power rating calculations
(2) The range of values indicates the effect of pc-board. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc-board where possible in order to spread the heat away form the device more effectively. For information on the PowerPAD™ package, refer to Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002) and Application Brief, PowerPad Made Easy, Texas Instruments (SLMA004).
(3) The PowerPAD™ is not directly connected to any leads of this package. However, it is electrically and thermally connected to the substrate which is the ground of the device.
UCC27423 UCC27424 UCC27425 switch_lus545.gif Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
UCC27423 UCC27424 UCC27425 switch2_lus545.gif

NOTE:

The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through the Miller regions of operation.
Figure 2. Switching Waveform for Enable to Output

7.7 Typical Characteristics

UCC27423 UCC27424 UCC27425 tc_supcur_lus545.gif Figure 3. Supply Current vs Frequency (VDD = 4.5 V)
UCC27423 UCC27424 UCC27425 tc_supcur2_lus545.gif Figure 5. Supply Current vs Frequency (VDD = 12 V)
UCC27423 UCC27424 UCC27425 tc_supcur4_lus545.gif Figure 7. Supply Current vs Supply Voltage
(CLOAD = 2.2 nF)
UCC27423 UCC27424 UCC27425 tc_supcur6_lus545.gif Figure 9. Supply Current vs Supply Voltage (UCC27423)
UCC27423 UCC27424 UCC27425 tc_supcur8_lus545.gif Figure 11. Supply Current vs Supply Voltage (UCC27425)
UCC27423 UCC27424 UCC27425 tc_rise1_lus545.gif Figure 13. Rise Time vs Supply Voltage
UCC27423 UCC27424 UCC27425 tc_delay_lus545.gif Figure 15. Delay Time (tD1) vs Supply Voltage (UCC27423)
UCC27423 UCC27424 UCC27425 tc_enab_lus545.gif Figure 17. Enable Threshold and Hysteresis vs Temperature
UCC27423 UCC27424 UCC27425 tc_output_lus545.gif Figure 19. Output Behavior vs Supply Voltage (Inverting)
UCC27423 UCC27424 UCC27425 tc_output2_lus545.gif Figure 21. Output Behavior vs VDD (Inverting)
UCC27423 UCC27424 UCC27425 tc_output4_lus545.gif Figure 23. Output Behavior vs VDD (Noninverting)
UCC27423 UCC27424 UCC27425 tc_output6_lus545.gif Figure 25. Output Behavior vs VDD (Noninverting)
UCC27423 UCC27424 UCC27425 tc_input_lus545.gif Figure 27. Input Threshold vs Temperature
UCC27423 UCC27424 UCC27425 tc_supcur1_lus545.gif Figure 4. Supply Current vs Frequency (VDD = 8.0 V)
UCC27423 UCC27424 UCC27425 tc_supcur3_lus545.gif Figure 6. Supply Current vs Frequency (VDD = 15 V)
UCC27423 UCC27424 UCC27425 tc_supcur5_lus545.gif Figure 8. Supply Current vs Supply Voltage
(CLOAD = 4.7 nF)
UCC27423 UCC27424 UCC27425 tc_supcur7_lus545.gif Figure 10. Supply Current vs Supply Voltage (UCC27424)
UCC27423 UCC27424 UCC27425 tc_rise_lus545.gif Figure 12. Rise Time and Fall Time
vs Temperature (UCC27423)
UCC27423 UCC27424 UCC27425 tc_fall_lus545.gif Figure 14. Fall Time vs Supply Voltage
UCC27423 UCC27424 UCC27425 tc_delay1_lus545.gif Figure 16. Delay Time (tD2) vs Supply Voltage (UCC27423)
UCC27423 UCC27424 UCC27425 tc_enab1_lus545.gif Figure 18. Enable Resistance vs Temperature
UCC27423 UCC27424 UCC27425 tc_output1_lus545.gif Figure 20. Output Behavior vs Supply Voltage (Inverting)
UCC27423 UCC27424 UCC27425 tc_output3_lus545.gif Figure 22. Output Behavior vs VDD (Inverting)
UCC27423 UCC27424 UCC27425 tc_output5_lus545.gif Figure 24. Output Behavior vs VDD (Noninverting)
UCC27423 UCC27424 UCC27425 tc_output7_lus545.gif Figure 26. Output Behavior vs VDD (Noninverting)