Table 4. UCC27714 Design Requirements

8.2.2.1 Selecting HI and LI Low Pass Filter Components (R_HI, R_LI, C_HI, C_LI)

A RC filter should be added between PWM controller and input pin of UCC27714 to filter the high frequency noise, like R_HI/C_HI and R_LI/C_LI which shown in Figure 54. The recommended values of the RC filter is refer to Equation 1 and Equation 2:

Equation 1.

Equation 2.

8.2.2.2 Selecting Bootstrap Capacitor (C_BOOT)

The bootstrap capacitor should be sized to have more than enough energy to drive the gate of FET Q1 high, without depleting the boot capacitor more than 10%. A good rule of thumb is size C_BOOT to be at least 10 times; as large as the equivalent FET gate capacitance (C_g).

C_g will have to be calculated based voltage driving the high side FET’s gate (V_Q1g ) and knowing the FET’s gate charge (Q_g).  V_Q1g is approximately the bias voltage supplied to VDD less the forward voltage drop of the boost diode (V_DBOOT).  In this design example, the estimated V_Q1g was approximately 11.4V

Equation 3.

The FET used in this example had a specified Q_g of 87 nC.  Based on Q_g and V_Q1g the calculated C_g was 7.63 nF.

Equation 4.

Once C_g is estimated C_BOOT should be sized to be at least 10 times larger than C_g.

Equation 5.

For this design example a 100-nF capacitor was chosen for the bootstrap capacitor.

Equation 6.

8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (C_VDD) and R_bias

The VDD capacitor (C_VDD) should be chosen to be at least 10 times larger than C_BOOT.  For this design example a 1-µF capacitor was selected.

Equation 7.

A 5-Ω resistor R_BIAS in series with bias supply and VDD pin is recommended to make the VDD ramp up time larger than 50 µs to prevent error logic error spikes on the outputs as shown in Figure 55

Figure 55. VDD/HB-HS Fast Ramp Up

8.2.2.4 Selecting Bootstrap Resistor (R_BOOT)

Resistor R_BOOT is selected to limit the current in D_BOOT and limit the ramp up slew rate of voltage of HB-HS to avoid the phenomenon shown in Figure 55.  It is recommended when using the UCC27714 that R_BOOT is between 2 Ω and 10 Ω.  For this design we selected a current limiting resistor of 2.2 Ω.  The bootstrap diode current (I_DBOOT(pk)) was limited to roughly 5.2 A.

Equation 8.

Equation 9.

The power dissipation capability of the bootstrap resistor is important. The bootstrap resistor must be able to withstand the short period of high power dissipation during the initial charging sequence of the boot-strap capacitor. This energy is equivalent to 1/2 × CBOOT × V². This energy is dissipated during the charging time of the bootstrap capacitor (~3 × R_BOOT × C_BOOT). Special attention must be paid to use a bigger size R_BOOT when a bigger value of C_BOOT is chosen.

8.2.2.5 Selecting Gate Resistor R_HO/R_LO

Resistor R_HO and R_LO are sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the current coming out of the gate driver.  For this design 3.01-Ω resistors were selected for this design.

Equation 10.

Maximum HO Drive Current (I_{HO_DR}):

Equation 11.

Maximum HO Sink Current (I_{HO_SK}):

Equation 12.

Maximum LO Drive Current (I_{LO_DR}):

Equation 13.

Maximum LO Sink Current (I_{LO_SK}):

Equation 14.

In applications with high dV/dt switching and/or significant ringing on the HS node, the HO output may exhibit a short duration pulse although the HI input is high for a longer time. MOSFET’s with slow body diode recovery time can result in high dV/dt transitions and excessive ringing in hard switching conditions. If the user observes this condition the problem can be corrected by increasing R_HO and R_LO to limit HS dV/dt and ringing to <50 V/ns dV_HS/dt specification of the UCC27714. Refer to Figure 56 below.

Figure 56. Increase R_HO and R_LO, Reduce HS dV/dt

8.2.2.6 Selecting Bootstrap Diode

A fast recovery diode should be chosen to avoid charge is taken away from the bootstrap capacitor. Thus, a fast reverse recovery time t_RR, low forward voltage V_F and low junction capacitance is recommended.

Suggested parts include MURA160T3G and BYG20J.

8.2.2.7 Estimate the UCC27714 Power Losses (P_UCC27714)

The power losses of UCC27714 (P_UCC27714) are estimated by calculating losses from several components:

The static power losses due to quiescent current (I_QDD, I_QBS) are calculated in Equation 15:

Equation 15.

Static losses due to leakage current (I_BL) are calculated from the HB high-voltage node as shown in Equation 16:

Equation 16.

Dynamic losses incurred due to the gate charge while driving the FETs Q1 and Q2 are calculated Equation 17. Please note that this component typically dominates over the dynamic losses related to the internal VDD & VHB switching logic circuitry in UCC27714.

Equation 17.

Equation 18 calculates dynamic losses during the operation of the level shifter at HO turn-off edge. Q_P, typically 0.5 nC, is the charge absorbed by the level shifter during operation at each edge. Please note that if high-voltage switching occurs during HO turn-on as well (as in the case of ZVS topologies), then the power loss due to this component must be effectively doubled.

Equation 18.

The total power losses are calculated in Equation 19:

Equation 19.

For the conditions, VDD=VBS=15V, VHB = VHS + VBS = 400V, HO On-state Duty cycle D = 50%, Q_G = 87nC, f_SW = 100kHz, the total power loss in UCC27714 driver for a ZVS power supply topology can be estimated as follows, assuming no external gate drive resistors are used in the design:

Equation 20.

When external resistors are used in the gate drive circuit, a portion of this power loss is incurred on these external resistors and the power loss in UCC27714 will be lower, allowing the device to run at lower temperatures.

8.2.2.8 Application Example Schematic Note

In the application example schematic there are 10-kΩ resistors across the gate and source terminals of FET Q1 and Q2.  These resistors are placed across these nodes to ensure FETs Q1 and Q2 are not turned on if the UCC27714 is not in place or properly soldered to the circuit board or if UCC27714 is in an unbiased state.

8.2.2.9 LO and HO Overshoot and Undershoot

The LO and HO driver outputs may exhibit output overshoot beyond the VDD or HB level or output undershoot below COM or HS. This overshoot and/or undershoot is typically due to the high di/dt during switch transition and parasitic inductance, including PC board trace inductance and device package inductance in the driver gate drive current loop. If the driver output overshoot or undershoot exceeds the datasheet limits of –0.3 V DC, –2 V for 100 ns, or VDD (VHB) +0.3 V, the driver output can be in the incorrect state. If the user observes the incorrect output behavior, the issue can be resolved by slowing down the di/dt and dv/dt by increasing the gate drive resistance, see Figure 56, or adding Schottky diodes to the HO and LO outputs to clamp the driver LO output to VDD and COM, and the HO output to HB and HS. Refer to Figure 57 below for diode placement. The diodes must be placed close to the IC pins and connected with short traces.

Figure 57. Driver Overshoot and Undershoot Clamp Diodes